Re: [PATCH net-next 0/5] net/mlx5: Add balance ID support for LAG multiplane groups

[Tariq Toukan]

On 26/10/2025 1:59, Zhu Yanjun wrote:
> 在 2025/10/23 2:16, Tariq Toukan 写道:
> > Hi,
> >
> > This series adds balance ID support for MLX5 LAG in multiplane
> > configurations.
> >
> > See detailed description by Mark below [1].
> >
> > Regards,
> > Tariq
> >
> >
> > [1]
> > The problem: In complex multiplane LAG setups, we need finer control 
> > over LAG
> > groups. Currently, devices with the same system image GUID are treated
> > identically, but hardware now supports per-multiplane-group balance 
> > IDs that
> > let us differentiate between them. On such systems image system guid
> > isn't enough to decide which devices should be part of which LAG.
> >
> > The solution: Extend the system image GUID with a balance ID byte when 
> > the
> > hardware supports it. This gives us the granularity we need without 
> > breaking
> > existing deployments.
> >
> > What this series does:
> >
> > 1. Add the hardware interface bits (load_balance_id and lag_per_mp_group)
> > 2. Clean up some duplicate code while we're here
> > 3. Rework the system image GUID infrastructure to handle variable lengths
> > 4. Update PTP clock pairing to use the new approach
> > 5. Restructure capability setting to make room for the new feature
> > 6. Actually implement the balance ID support
> >
> > The key insight is in patch 6: we only append the balance ID when both
>
> In the above, patch 6 is the following patch? It should be patch 5?
>
> [PATCH net-next 5/5] net/mlx5: Add balance ID support for LAG multiplane 
> groups
>
> Yanjun.Zhu

Right.

Indices shifted because we sent the preparation IFC patch a priori:
137d1a635513 net/mlx5: IFC add balance ID and LAG per MP group bits

> > capabilities are present, so older hardware and software continue to work
> > exactly as before. For newer setups, you get the extra byte that enables
> > per-multiplane-group load balancing.
> >
> > This has been tested with both old and new hardware configurations.
> >
> >
> > Mark Bloch (5):
> >    net/mlx5: Use common mlx5_same_hw_devs function
> >    net/mlx5: Add software system image GUID infrastructure
> >    net/mlx5: Refactor PTP clock devcom pairing
> >    net/mlx5: Refactor HCA cap 2 setting
> >    net/mlx5: Add balance ID support for LAG multiplane groups
> >
> >   drivers/net/ethernet/mellanox/mlx5/core/dev.c | 12 ++++---
> >   .../ethernet/mellanox/mlx5/core/en/devlink.c  |  7 ++--
> >   .../ethernet/mellanox/mlx5/core/en/mapping.c  | 13 +++++---
> >   .../ethernet/mellanox/mlx5/core/en/mapping.h  |  3 +-
> >   .../mellanox/mlx5/core/en/rep/bridge.c        |  6 +---
> >   .../mellanox/mlx5/core/en/tc/int_port.c       |  8 +++--
> >   .../ethernet/mellanox/mlx5/core/en/tc_ct.c    | 11 ++++---
> >   .../net/ethernet/mellanox/mlx5/core/en_tc.c   | 32 ++++++++++---------
> >   .../mellanox/mlx5/core/esw/devlink_port.c     |  6 +---
> >   .../mellanox/mlx5/core/eswitch_offloads.c     |  8 +++--
> >   .../net/ethernet/mellanox/mlx5/core/lag/lag.c |  4 ++-
> >   .../ethernet/mellanox/mlx5/core/lib/clock.c   | 19 ++++++-----
> >   .../ethernet/mellanox/mlx5/core/lib/devcom.h  |  2 ++
> >   .../net/ethernet/mellanox/mlx5/core/main.c    | 23 +++++++++----
> >   .../ethernet/mellanox/mlx5/core/mlx5_core.h   |  2 ++
> >   .../net/ethernet/mellanox/mlx5/core/vport.c   | 19 +++++++++++
> >   include/linux/mlx5/driver.h                   |  3 ++
> >   17 files changed, 112 insertions(+), 66 deletions(-)
> >
> >
> > base-commit: d550d63d0082268a31e93a10c64cbc2476b98b24