RE: [PATCH 01/10] clk: renesas: r9a09g077: add TSU module clock

[Cosmin-Gabriel Tanislav]

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: Monday, October 27, 2025 12:45 PM
> To: Cosmin-Gabriel Tanislav <cosmin-gabriel.tanislav.xa@xxxxxxxxxxx>
> Cc: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>; Rafael J . Wysocki <rafael@xxxxxxxxxx>; Daniel Lezcano
> <daniel.lezcano@xxxxxxxxxx>; Zhang Rui <rui.zhang@xxxxxxxxx>; Lukasz Luba <lukasz.luba@xxxxxxx>; Rob
> Herring <robh@xxxxxxxxxx>; Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley
> <conor+dt@xxxxxxxxxx>; Geert Uytterhoeven <geert+renesas@xxxxxxxxx>; magnus.damm
> <magnus.damm@xxxxxxxxx>; Michael Turquette <mturquette@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>;
> Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>; linux-pm@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; linux-renesas-soc@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH 01/10] clk: renesas: r9a09g077: add TSU module clock
> 
> On Thu, 23 Oct 2025 at 10:20, Cosmin Tanislav
> <cosmin-gabriel.tanislav.xa@xxxxxxxxxxx> wrote:
> > The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a TSU
> > peripheral with controlled by a module clock.
> >
> > The TSU module clock is enabled in register MSTPCRG (0x30c), at bit 7,
> 
> MSTPCRD
> 
> I will fix that while applying.
> 

Thank you for spotting this, I double checked and indeed it's
MSTPCRD not MSTPCRG.

> > resulting in a (0x30c - 0x300) / 4 * 100 + 7 = 307 index.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds