Re: [PATCH v2] drm/ttm: add pgprot handling for RISC-V

[Han Gao]

Tested on sophgo sg2042/sophgo sg2044/ultrarisc dp1000.

On Mon, Oct 27, 2025 at 3:57 PM Christian König
<christian.koenig@xxxxxxx> wrote:
>
>
>
> On 10/20/25 07:35, Icenowy Zheng wrote:
> > The RISC-V Svpbmt privileged extension provides support for overriding
> > page memory coherency attributes, and, along with vendor extensions like
> > Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
> >
> > Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
> > and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
> > access attributes.
> >
> > Signed-off-by: Icenowy Zheng <uwu@xxxxxxxxxx>
> > Tested-by: Han Gao <rabenda.cn@xxxxxxxxx>
> > ---
> > Changes in v2:
> > - Added Han Gao's test tag.
> >
> >  drivers/gpu/drm/ttm/ttm_module.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
> > index b3fffe7b5062a..aa137ead5cc59 100644
> > --- a/drivers/gpu/drm/ttm/ttm_module.c
> > +++ b/drivers/gpu/drm/ttm/ttm_module.c
> > @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
> >  #endif /* CONFIG_UML */
> >  #endif /* __i386__ || __x86_64__ */
> >  #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> > -     defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
> > +     defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
> > +     defined(__riscv)
>
> Looks reasonable, but does that work on all RISC-V variants?
>
> And while at it maybe please fix the indentation, using a tab here is probably not very adequate. In other words make the defined() match the one on the first line.
>
> Regards,
> Christian.
>
> >       if (caching == ttm_write_combined)
> >               tmp = pgprot_writecombine(tmp);
> >       else
>