Re: [PATCH v2 4/5] clk: amlogic: Optimize PLL enable timing
From: Chuan Liu
Date: Thu Oct 30 2025 - 05:24:07 EST
Hi Jerome,
On 10/30/2025 4:38 PM, Jerome Brunet wrote:
[ EXTERNAL EMAIL ]
On Thu 30 Oct 2025 at 13:24, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@xxxxxxxxxx> wrote:
From: Chuan Liu <chuan.liu@xxxxxxxxxxx>
l_detect controls the enablement of the PLL lock detection module.
It should remain disabled while the internal PLL circuits are
reaching a steady state; otherwise, the lock signal may be falsely
triggered high.
Before enabling the internal power supply of the PLL, l_detect should
be disabled. After the PLL’s internal circuits have stabilized,
l_detect should be enabled to prevent false lock signal triggers.
You to reformat this description. It feel that both paragraph are saying
the same thing.
Ok, drop it.
Currently, only A1 supports both l_detect and current_en, so this
patch will only affect A1.
Signed-off-by: Chuan Liu <chuan.liu@xxxxxxxxxxx>
---
drivers/clk/meson/clk-pll.c | 28 +++++++++++++++-------------
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 6c794adb8ccd..c6eebde1f516 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -383,36 +383,38 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
+ /* Disable the PLL lock-detect module */
+ if (MESON_PARM_APPLICABLE(&pll->l_detect))
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+
/* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1);
/* Wait for Bandgap and LDO to power up and stabilize */
udelay(20);
- /* Take the pll out reset */
- if (MESON_PARM_APPLICABLE(&pll->rst))
- meson_parm_write(clk->map, &pll->rst, 0);
Why is the reset moving around ? nothing is said in the description about
that
The function of current_en in the PLL is similar to en. It's more
reliable to assert the reset signal after current_en is set high.
I'll update the commit description accordingly in the next version.
-
- /* Wait for PLL loop stabilization */
- udelay(20);
-
/*
* Compared with the previous SoCs, self-adaption current module
* is newly added for A1, keep the new power-on sequence to enable the
* PLL. The sequence is:
- * 1. enable the pll, delay for 10us
+ * 1. enable the pll, delay for 20us
* 2. enable the pll self-adaption current module, delay for 40us
* 3. enable the lock detect module
*/
if (MESON_PARM_APPLICABLE(&pll->current_en)) {
- udelay(10);
meson_parm_write(clk->map, &pll->current_en, 1);
- udelay(40);
+ udelay(20);
}
- if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
- meson_parm_write(clk->map, &pll->l_detect, 1);
+ /* Take the pll out reset */
+ if (MESON_PARM_APPLICABLE(&pll->rst))
+ meson_parm_write(clk->map, &pll->rst, 0);
+
+ /* Wait for PLL loop stabilization */
+ udelay(20);
+
+ /* Enable the lock-detect module */
+ if (MESON_PARM_APPLICABLE(&pll->l_detect))
meson_parm_write(clk->map, &pll->l_detect, 0);
- }
if (meson_clk_pll_wait_lock(hw)) {
/* disable PLL when PLL lock failed. */
--
Jerome