Re: [PATCH v2 2/5] clk: amlogic: Improve the issue of PLL lock failures

[Chuan Liu]

Hi Jerome,

On 10/30/2025 4:41 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu 30 Oct 2025 at 13:24, Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@xxxxxxxxxx> wrote:
>
> > From: Chuan Liu <chuan.liu@xxxxxxxxxxx>
> >
> > Due to factors such as temperature and process variations, the
> > internal circuits of the PLL may require a longer time to reach a
> > steady state, which can result in occasional lock failures on some
> > SoCs under low-temperature conditions.
> >
> > After enabling the PLL and releasing its reset, a 20 us delay is
> > added at each step to provide enough time for the internal PLL
> > circuit to stabilize, thus reducing the probability of PLL lock
> > failure.
> >
> > Signed-off-by: Chuan Liu <chuan.liu@xxxxxxxxxxx>
> > ---
> >   drivers/clk/meson/clk-pll.c | 5 +++++
> >   1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
> > index 629f6af18ea1..f81ebf6cc981 100644
> > --- a/drivers/clk/meson/clk-pll.c
> > +++ b/drivers/clk/meson/clk-pll.c
> > @@ -368,11 +368,16 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
> >
> >        /* Enable the pll */
> >        meson_parm_write(clk->map, &pll->en, 1);
>
> New line

Ok, fix it in the next version.

> > +     /* Wait for Bandgap and LDO to power up and stabilize */
> > +     udelay(20);
> >
> >        /* Take the pll out reset */
> >        if (MESON_PARM_APPLICABLE(&pll->rst))
> >                meson_parm_write(clk->map, &pll->rst, 0);
> >
> > +     /* Wait for PLL loop stabilization */
> > +     udelay(20);
> > +
> >        /*
> >         * Compared with the previous SoCs, self-adaption current module
> >         * is newly added for A1, keep the new power-on sequence to enable the
>
> --
> Jerome