Re: [PATCH net-next 1/4] net: stmmac: socfpga: Agilex5 EMAC platform configuration

[G Thomas, Rohan]

Hi Maxime,

On 10/29/2025 7:04 PM, Maxime Chevallier wrote:
> Hi Rohan,
>
> On 29/10/2025 09:06, Rohan G Thomas via B4 Relay wrote:
> > From: Rohan G Thomas <rohan.g.thomas@xxxxxxxxxx>
> >
> > Agilex5 HPS EMAC uses the dwxgmac-3.10a IP, unlike previous socfpga
> > platforms which use dwmac1000 IP. Due to differences in platform
> > configuration, Agilex5 requires a distinct setup.
> >
> > Introduce a setup_plat_dat() callback in socfpga_dwmac_ops to handle
> > platform-specific setup. This callback is invoked before
> > stmmac_dvr_probe() to ensure the platform data is correctly
> > configured. Also, implemented separate setup_plat_dat() callback for
> > current socfpga platforms and Agilex5.
> >
> > Signed-off-by: Rohan G Thomas <rohan.g.thomas@xxxxxxxxxx>
> > ---
> >   .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    | 53 ++++++++++++++++++----
> >   1 file changed, 43 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> > index 2ff5db6d41ca08a1652d57f3eb73923b9a9558bf..3dae4f3c103802ed1c2cd390634bd5473192d4ee 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> > @@ -44,6 +44,7 @@
> >   struct socfpga_dwmac;
> >   struct socfpga_dwmac_ops {
> >   	int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv);
> > +	void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);
> >   };
> >   
> >   struct socfpga_dwmac {
> > @@ -441,6 +442,39 @@ static int socfpga_dwmac_init(struct platform_device *pdev, void *bsp_priv)
> >   	return dwmac->ops->set_phy_mode(dwmac);
> >   }
> >   
> > +static void socfpga_common_plat_dat(struct socfpga_dwmac *dwmac)
> > +{
> > +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
> > +
> > +	plat_dat->bsp_priv = dwmac;
> > +	plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
> > +	plat_dat->init = socfpga_dwmac_init;
> > +	plat_dat->pcs_init = socfpga_dwmac_pcs_init;
> > +	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
> > +	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
> > +}
> > +
> > +static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
> > +{
> > +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
> > +
> > +	socfpga_common_plat_dat(dwmac);
> > +
> > +	plat_dat->core_type = DWMAC_CORE_GMAC;
> > +
> > +	/* Rx watchdog timer in dwmac is buggy in this hw */
> > +	plat_dat->riwt_off = 1;
> > +}
> > +
> > +static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
> > +{
> > +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
> > +
> > +	socfpga_common_plat_dat(dwmac);
>
> I"m not familiar with this device (I only have a Cyclone V on hand), does
> it still make sense to try to instantiate a Lynx (i.e. Altera TSE) PCS
> for that IP ?

AFAIK, yes it is supported by Agilex V device family also.
https://www.altera.com/products/ip/a1jui0000049uuomam/triple-speed-ethernet-fpga-ip

> Maxime

Best Regards,
Rohan