Re: [PATCH v7 2/8] x86/mce: Unify AMD DFR handler with MCA Polling

[Borislav Petkov]

On Mon, Oct 27, 2025 at 10:11:39AM -0400, Yazen Ghannam wrote:
>  	/*
> -	 * If the MCA_STATUS register has a deferred error, then continue using it as
> -	 * the status register.
> -	 *
> -	 * MCA_DESTAT will be cleared at the end of the handler.
> +	 * If MCA_STATUS happens to have a deferred error, then MCA_DESTAT will
> +	 * be cleared at the end of the handler.
>  	 */
> -	if ((m->status & MCI_STATUS_VAL) && (m->status & MCI_STATUS_DEFERRED))
> +	if (m->status & MCI_STATUS_VAL)
>  		return true;

I'm still confused by those comments - we check VAL but we talk about
deferred...

>  
>  	/*
> -	 * If the MCA_DESTAT register has a deferred error, then use it instead.
> +	 * Use the MCA_DESTAT register if it has a deferred error.

This one...

> The redundant
> +	 * status bit check is to filter out any bogus errors.

... probably only confuses. No need to mention it.

>  	 *
>  	 * MCA_STATUS will not be cleared at the end of the handler.
>  	 */
> @@ -780,7 +777,7 @@ static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err)
>  	struct mce *m = &err->m;
>  
>  	if (mce_flags.smca)
> -		return smca_should_log_poll_error(flags, err);
> +		return smca_should_log_poll_error(m);
>  
>  	/* If this entry is not valid, ignore it. */
>  	if (!(m->status & MCI_STATUS_VAL))

-- 
Regards/Gruss,
    Boris.

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