RE: [PATCH 01/14] clk: renesas: r9a09g077: add SPI module clocks

[Cosmin-Gabriel Tanislav]

> -----Original Message-----
> From: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@xxxxxxxxxxx>
> Sent: Tuesday, October 28, 2025 3:32 PM
> Cc: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>; Mark Brown <broonie@xxxxxxxxxx>; Rob Herring
> <robh@xxxxxxxxxx>; Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>; Geert
> Uytterhoeven <geert+renesas@xxxxxxxxx>; magnus.damm <magnus.damm@xxxxxxxxx>; Michael Turquette
> <mturquette@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>; Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>;
> linux-spi@xxxxxxxxxxxxxxx; linux-renesas-soc@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; Cosmin-Gabriel Tanislav <cosmin-
> gabriel.tanislav.xa@xxxxxxxxxxx>
> Subject: [PATCH 01/14] clk: renesas: r9a09g077: add SPI module clocks
> 
> The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have four SPI
> peripherals, each with their own clock divider, which divides PLL4 by
> either 24, 25, 30 or 32, similar to the SCI peripheral.
> 
> The dividers feed into the usual module clocks.
> 
> Add them all.
> 
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@xxxxxxxxxxx>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>

My bad, these were left over from our internal review. I'll remove them
in the next version.

> ---
>  drivers/clk/renesas/r9a09g077-cpg.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
> index 79083165537c..0f61e0f09697 100644
> --- a/drivers/clk/renesas/r9a09g077-cpg.c
> +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> @@ -54,6 +54,11 @@
>  #define DIVSCI3ASYNC	CONF_PACK(SCKCR3, 12, 2)
>  #define DIVSCI4ASYNC	CONF_PACK(SCKCR3, 14, 2)
> 
> +#define DIVSPI0ASYNC	CONF_PACK(SCKCR3, 0, 2)
> +#define DIVSPI1ASYNC	CONF_PACK(SCKCR3, 2, 2)
> +#define DIVSPI2ASYNC	CONF_PACK(SCKCR3, 4, 2)
> +#define DIVSPI3ASYNC	CONF_PACK(SCKCR2, 16, 2)
> +
>  #define SEL_PLL		CONF_PACK(SCKCR, 22, 1)
> 
> 
> @@ -94,6 +99,10 @@ enum clk_ids {
>  	CLK_SCI3ASYNC,
>  	CLK_SCI4ASYNC,
>  	CLK_SCI5ASYNC,
> +	CLK_SPI0ASYNC,
> +	CLK_SPI1ASYNC,
> +	CLK_SPI2ASYNC,
> +	CLK_SPI3ASYNC,
> 
>  	/* Module Clocks */
>  	MOD_CLK_BASE,
> @@ -154,6 +163,15 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
>  	DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC,
>  		dtable_24_25_30_32),
> 
> +	DEF_DIV(".spi0async", CLK_SPI0ASYNC, CLK_PLL4D1, DIVSPI0ASYNC,
> +		dtable_24_25_30_32),
> +	DEF_DIV(".spi1async", CLK_SPI1ASYNC, CLK_PLL4D1, DIVSPI1ASYNC,
> +		dtable_24_25_30_32),
> +	DEF_DIV(".spi2async", CLK_SPI2ASYNC, CLK_PLL4D1, DIVSPI2ASYNC,
> +		dtable_24_25_30_32),
> +	DEF_DIV(".spi3async", CLK_SPI3ASYNC, CLK_PLL4D1, DIVSPI3ASYNC,
> +		dtable_24_25_30_32),
> +
>  	/* Core output clk */
>  	DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
>  		dtable_1_2),
> @@ -192,6 +210,9 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
>  	DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
>  	DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
>  	DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
> +	DEF_MOD("spi0", 104, CLK_SPI0ASYNC),
> +	DEF_MOD("spi1", 105, CLK_SPI1ASYNC),
> +	DEF_MOD("spi2", 106, CLK_SPI2ASYNC),
>  	DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
>  	DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
>  	DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
> @@ -204,6 +225,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
>  	DEF_MOD("gmac2", 417, R9A09G077_CLK_PCLKAM),
>  	DEF_MOD("sci5fck", 600, CLK_SCI5ASYNC),
>  	DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
> +	DEF_MOD("spi3", 602, CLK_SPI3ASYNC),
>  	DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
>  	DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
>  };
> --
> 2.51.1