RE: [PATCH RESEND v4 2/2] dmaengine: dw-edma: Add non-LL mode
From: Verma, Devendra
Date: Tue Oct 28 2025 - 07:38:23 EST
[AMD Official Use Only - AMD Internal Distribution Only]
Thank you Manivannan for reviewing the patches!
Please check my response inline.
Regards,
Devendra
> -----Original Message-----
> From: Manivannan Sadhasivam <mani@xxxxxxxxxx>
> Sent: Monday, October 27, 2025 6:45 PM
> To: Verma, Devendra <Devendra.Verma@xxxxxxx>
> Cc: bhelgaas@xxxxxxxxxx; vkoul@xxxxxxxxxx; dmaengine@xxxxxxxxxxxxxxx;
> linux-pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Simek, Michal
> <michal.simek@xxxxxxx>
> Subject: Re: [PATCH RESEND v4 2/2] dmaengine: dw-edma: Add non-LL mode
>
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
>
>
> On Tue, Oct 14, 2025 at 05:46:34PM +0530, Devendra K Verma wrote:
> > AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.
>
> Isn't the patch adding non-LL mode for all platforms, not just for AMD?
>
A specific case where LL mode is enabled, which is the default mode, in
this case all the IPs can support the non-LL mode provided it shall be
configured via the config param peripheral_config by the client.
The default case where non-LL mode is enabled for all the IPs is NOT
supported by all the IPs.
> > The current code does not have the mechanisms to enable the DMA
> > transactions using the non-LL mode. The following two cases are added
> > with this patch:
> > - When a valid physical base address is not configured via the
> > Xilinx VSEC capability then the IP can still be used in non-LL
> > mode. The default mode for all the DMA transactions and for all
> > the DMA channels then is non-LL mode.
> > - When a valid physical base address is configured but the client
> > wants to use the non-LL mode for DMA transactions then also the
> > flexibility is provided via the peripheral_config struct member of
> > dma_slave_config. In this case the channels can be individually
> > configured in non-LL mode. This use case is desirable for single
> > DMA transfer of a chunk, this saves the effort of preparing the
> > Link List.
> >
> > Signed-off-by: Devendra K Verma <devendra.verma@xxxxxxx>
> > ---
> > Changes in v4
> > No change
> >
> > Changes in v3
> > No change
> >
> > Changes in v2
> > Reverted the function return type to u64 for
> > dw_edma_get_phys_addr().
> >
> > Changes in v1
> > Changed the function return type for dw_edma_get_phys_addr().
> > Corrected the typo raised in review.
> > ---
> > drivers/dma/dw-edma/dw-edma-core.c | 38 ++++++++++++++++++---
> > drivers/dma/dw-edma/dw-edma-core.h | 1 +
> > drivers/dma/dw-edma/dw-edma-pcie.c | 44 +++++++++++++++++--------
> > drivers/dma/dw-edma/dw-hdma-v0-core.c | 62
> ++++++++++++++++++++++++++++++++++-
> > include/linux/dma/edma.h | 1 +
> > 5 files changed, 127 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/dma/dw-edma/dw-edma-core.c
> > b/drivers/dma/dw-edma/dw-edma-core.c
> > index b43255f..3283ac5 100644
> > --- a/drivers/dma/dw-edma/dw-edma-core.c
> > +++ b/drivers/dma/dw-edma/dw-edma-core.c
> > @@ -223,8 +223,28 @@ static int dw_edma_device_config(struct
> dma_chan *dchan,
> > struct dma_slave_config *config) {
> > struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
> > + int nollp = 0;
>
> s/nollp/non_ll
>
Suggestion accepted. Thanks!
> > +
> > + if (WARN_ON(config->peripheral_config &&
> > + config->peripheral_size != sizeof(int)))
>
> Use proper dev_err(), not WARN_ON.
>
Suggestion accepted, dev_err() replaces WARN_ON() in latest drop.
Thanks!
> > + return -EINVAL;
> >
> > memcpy(&chan->config, config, sizeof(*config));
> > +
> > + /*
> > + * When there is no valid LLP base address available
> > + * then the default DMA ops will use the non-LL mode.
> > + * Cases where LL mode is enabled and client wants
> > + * to use the non-LL mode then also client can do
> > + * so via providing the peripheral_config param.
>
> Make use of 80 columns for comments throughout this patch.
>
Comments follow the 80-column guideline. Thanks!
> Rest LGTM!
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்