[PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

[Khairul Anuar Romli]

Introduce the Stratix10 SoC service layer (SVC) node for Agilex5 SoCs.
The node includes the compatible string "intel,agilex5-svc" and references
a reserved memory region required for communication with the Secure Device
Manager (SDM).

Agilex5 introduces a dependency on IOMMU-based translation for reserved
memory, unlike prior Agilex platforms. This commit introduces the
structural changes needed to support this feature once the IOMMU driver
is upstreamed.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@xxxxxxxxxx>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a13ccee3c4c3..15284092897e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -841,5 +841,14 @@ queue7 {
 				};
 			};
 		};
+
+		firmware {
+			svc {
+				compatible = "intel,agilex5-svc";
+				method = "smc";
+				memory-region = <&service_reserved>;
+				iommus = <&smmu 10>;
+			};
+		};
 	};
 };
-- 
2.43.7