Re: [PATCH v2 3/7] dt-bindings: pci: spacemit: introduce PCIe host controller
From: Alex Elder
Date: Wed Oct 29 2025 - 20:10:10 EST
On 10/28/25 12:58 AM, Manivannan Sadhasivam wrote:
On Mon, Oct 27, 2025 at 05:24:33PM -0500, Alex Elder wrote:
On 10/26/25 11:38 AM, Manivannan Sadhasivam wrote:
On Mon, Oct 13, 2025 at 10:35:20AM -0500, Alex Elder wrote:
Add the Device Tree binding for the PCIe root complex found on the
SpacemiT K1 SoC. This device is derived from the Synopsys Designware
PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2
link speeds (5 GT/sec). One of the ports uses a combo PHY, which is
typically used to support a USB 3 port.
Signed-off-by: Alex Elder <elder@xxxxxxxxxxxx>
---
v2: - Renamed the binding, using "host controller"
- Added '>' to the description, and reworded it a bit
- Added reference to /schemas/pci/snps,dw-pcie.yaml
- Fixed and renamed the compatible string
- Renamed the PMU property, and fixed its description
- Consistently omit the period at the end of descriptions
- Renamed the "global" clock to be "phy"
- Use interrupts rather than interrupts-extended, and name the
one interrupt "msi" to make clear its purpose
- Added a vpcie3v3-supply property
- Dropped the max-link-speed property
- Changed additionalProperties to unevaluatedProperties
- Dropped the label and status property from the example
.../bindings/pci/spacemit,k1-pcie-host.yaml | 156 ++++++++++++++++++
1 file changed, 156 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
new file mode 100644
index 0000000000000..87745d49c53a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCI Express Host Controller
. . .
+ interrupt-names:
+ const: msi
+
+ phys:
+ maxItems: 1
+
+ vpcie3v3-supply:
+ description:
+ A phandle for 3.3v regulator to use for PCIe
Could you please move these Root Port specific properties (phy, vpcie3v3-supply)
to the Root Port node?
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
OK, I'll try to follow what that ST binding does (and the
matching driver).
For handling the 'vpcie3v3-supply', you can rely on PCI_PWRCTRL_SLOT driver.I looked at the code under pci/pwrctrl. But is there some other
documentation I should be looking at for this?
Sorry, nothing available atm. But I will create one, once we fix some core
issues with pwrctrl so that it becomes useable for all (more in the driver
patch).
Sounds good, I think it's necessary. I might not get it completely
right on the next try but I trust you'll help me understand what I
need to do.
It looks like it involves creating a new node compatible with
"pciclass,0604". And that the purpose of that driver was to
ensure certain resources are enabled before the "real" PCI
device gets probed.
I see two arm64 DTS files using it: x1e80100.dtsi and r8a779g0.dtsi.
Both define this node inside the main PCIe controller node.
Will this model (with the parent pwrctrl node and child PCI
controller node) be used for all PCI controllers from here on?
The PCI controller (host bridge) node is the parent and the Root Port node
(which gets bind to pwrctrl slot driver) will be the child.
That makes sense to me.
Or are you saying this properly represents the relationship of
the supply with the PCIe port in this SpacemiT case?
We want to use this for all the new platforms and also try to convert the old
ones too gradually.
OK, understood.
Thank you.
-Alex
- Mani