Re: [PATCH] KVM: x86: SVM: Mark VMCB_LBR dirty when L1 sets DebugCtl[LBR]

[Jim Mattson]

On Mon, Nov 3, 2025 at 9:42 AM Yosry Ahmed <yosry.ahmed@xxxxxxxxx> wrote:
>
> On Fri, Oct 31, 2025 at 05:02:29PM -0700, Jim Mattson wrote:
> > With the VMCB's LBR_VIRTUALIZATION_ENABLE bit set, the CPU will load
> > the DebugCtl MSR from the VMCB's DBGCTL field at VMRUN. To ensure that
> > it does not load a stale cached value, clear the VMCB's LBR clean bit
> > when L1 is running and bit 0 (LBR) of the DBGCTL field is changed from
> > 0 to 1. (Note that this is already handled correctly when L2 is
> > running.)
> >
> > There is no need to clear the clean bit in the other direction,
> > because when the VMCB's DBGCTL.LBR is 0, the VMCB's
> > LBR_VIRTUALIZATION_ENABLE bit will be clear, and the CPU will not
> > consult the VMCB's DBGCTL field at VMRUN.
>
> Is it worth the mental load of figuring out why we do it in
> svm_enable_lbrv() but not svm_disable_lbrv()?
>
> Maybe we can at least document it in svm_disable_lbrv() with a comment?

I'm happy to do it in svm_disable_lbrv() as well, just to reduce the
cognitive load.