Re: [PATCH v1 2/3] spi: dt-binding: document Microchip CoreSPI

[Krzysztof Kozlowski]

On 03/11/2025 17:05, Prajna Rajendra Kumar wrote:
> Add device tree bindings for Microchip's CoreSPI controller.
> 
> CoreSPI is a "soft" IP core intended for FPGA implementations. Its
> configurations are set in Libero. These properties represent
> non-discoverable configurations determined by Verilog parameters to the
> IP.
> 
> Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@xxxxxxxxxxxxx>
> ---
>  .../bindings/spi/microchip,mpfs-spi.yaml      | 65 +++++++++++++++++++
>  1 file changed, 65 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> index 62a568bdbfa0..62c38d0c93e7 100644
> --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> @@ -26,6 +26,7 @@ properties:
>            - const: microchip,pic64gx-spi
>            - const: microchip,mpfs-spi
>        - const: microchip,mpfs-spi
> +      - const: microchip,corespi-rtl-v5 # FPGA CoreSPI

Please keep alphabetical order. Or better, combine such (you have there
already!) into enum.


Best regards,
Krzysztof