Re: [PATCH v3 2/4] clk: amlogic: Improve the issue of PLL lock failures

[Martin Blumenstingl]

On Fri, Oct 31, 2025 at 9:10 AM Chuan Liu via B4 Relay
<devnull+chuan.liu.amlogic.com@xxxxxxxxxx> wrote:
>
> From: Chuan Liu <chuan.liu@xxxxxxxxxxx>
>
> Due to factors such as temperature and process variations, the
> internal circuits of the PLL may require a longer time to reach a
> steady state, which can result in occasional lock failures on some
> SoCs under low-temperature conditions.
>
> After enabling the PLL and releasing its reset, a 20 us delay is
> added at each step to provide enough time for the internal PLL
> circuit to stabilize, thus reducing the probability of PLL lock
> failure.
>
> Signed-off-by: Chuan Liu <chuan.liu@xxxxxxxxxxx>
Tested-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> # Odroid-C1