Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Andrew Lunn]

> Each of these IPs has its own link status pin as an input to the SoC:

> The above architecture is for the RZ/N1 SoC. For RZ/T2H SoC we dont
> have a SERCOS Controller. So in the case of RZ/T2H EVK the
> SWITCH_MII_LINK status pin is connected to the LED1 of VSC8541 PHY.
> 
> The PHYLNK register [0] (section 10.2.5 page 763) allows control of
> the active level of the link.
> 0: High active (Default)
> 1: Active Low
> 
> For example the SWITCH requires link-up to be reported to the switch
> via the SWITCH_MII_LINK input pin.

Why does the switch require this? The switch also needs to know the
duplex, speed etc. Link on its own is of not enough. So when phylink
mac_link_up is called, you tell it the speed, duplex and also that the
link is up. When the link goes down, mac_link_down callback will be
called and you tell it the link is down.

    Andrew