RE: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets

[Biju Das]

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 13 November 2025 19:39
> Subject: Re: [PATCH 01/19] clk: renesas: r9a09g047: Add RSCI clocks/resets
> 
> Hi Biju,
> 
> On Thu, 13 Nov 2025 at 20:35, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> On Mon, 27 Oct 2025
> > > at 16:46, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > > Add RSCI clock and reset entries.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > >
> > > > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > > > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> > > > @@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> > > >                                                 BUS_MSTOP(5, BIT(13))),
> > > >         DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
> > > >                                                 BUS_MSTOP(5,
> > > > BIT(13))),
> > > > +       DEF_MOD("rsci0_pclk",                   CLK_PLLCM33_DIV16, 5, 13, 2, 29,
> > > > +                                               BUS_MSTOP(11, BIT(3))),
> > > > +       DEF_MOD("rsci0_tclk",                   CLK_PLLCM33_DIV16, 5, 14, 2, 30,
> > > > +                                               BUS_MSTOP(11,
> > > > + BIT(3))),
> > >
> > > According to both the clock list and the clock system diagram, the
> > > parent clock of rsciN_pclk and rsciN_tclk is CLK_PLLCLN_DIV16?
> >
> > Thanks, you are correct, I will fix this in next version.
> 
> Thanks for confirming!
> I will fix it while applying, i.e. will queue in renesas-clk for v6.19.

Thank you for taking care of it.

Cheers,
Biju