Re: [PATCH v2] schemas: pci: Document PCIe T_POWER_ON

From: Krishna Chaitanya Chundru

Date: Thu Nov 13 2025 - 02:48:13 EST




On 11/10/2025 5:33 PM, Manivannan Sadhasivam wrote:
On Mon, Nov 10, 2025 at 04:59:47PM +0530, Krishna Chaitanya Chundru wrote:
From PCIe r6, sec 5.5.4 & Table 5-11 in sec 5.5.5 T_POWER_ON is the
minimum amount of time(in us) that each component must wait in L1.2.Exit
after sampling CLKREQ# asserted before actively driving the interface to
ensure no device is ever actively driving into an unpowered component and
these values are based on the components and AC coupling capacitors used
in the connection linking the two components.

This property should be used to indicate the T_POWER_ON for each Root Port.

I'm not sure if we should restrict this property to just Root Ports. Defining a
property in 'pci-bus-common.yaml' means, all PCI bridges could use it, but this
value is applicable to endpoint devices also.
Better to add in pci-device.yaml then.
Also, you might want to add some info that the driver (or DT consumer) should
derive the T_POWER_ON Scale and T_POWER_ON Value from this value.
ack

- Krishna Chaitanya.
- Mani

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
---
Changes in v1:
- Updated the commiit text (Mani).
- Link to v1: https://lore.kernel.org/all/20251110112550.2070659-1-krishna.chundru@xxxxxxxxxxxxxxxx/#t

dtschema/schemas/pci/pci-bus-common.yaml | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
index 5257339..bbe5510 100644
--- a/dtschema/schemas/pci/pci-bus-common.yaml
+++ b/dtschema/schemas/pci/pci-bus-common.yaml
@@ -152,6 +152,15 @@ properties:
This property is invalid in host bridge nodes.
maxItems: 1
+ t-power-on-us:
+ description:
+ The minimum amount of time that each component must wait in
+ L1.2.Exit after sampling CLKREQ# asserted before actively driving
+ the interface to ensure no device is ever actively driving into an
+ unpowered component. This value is based on the components and AC
+ coupling capacitors used in the connection linking the two
+ components(PCIe r6.0, sec 5.5.4).
+
supports-clkreq:
description:
If present this property specifies that CLKREQ signal routing exists from
--
2.34.1