[GIT PULL] EDAC urgent for v6.18-rc6

[Borislav Petkov]

Hi Linus,

please pull the urgent EDAC lineup for v6.18-rc6.

Thx.

---

The following changes since commit 79c0a2b7abc906c7cf3c793256c6b638d7dc477f:

  EDAC/versalnet: Fix off by one in handle_error() (2025-10-13 17:14:47 +0200)

are available in the Git repository at:

  ssh://git@xxxxxxxxxxxxxxxxxxx/pub/scm/linux/kernel/git/ras/ras.git tags/edac_urgent_for_v6.18_rc6

for you to fetch changes up to 281326be67252ac5794d1383f67526606b1d6b13:

  EDAC/altera: Use INTTEST register for Ethernet and USB SBE injection (2025-11-11 14:59:04 +0100)

----------------------------------------------------------------
- In Versalnet, handle the reporting of non-standard hw errors whose
  information can come in more than one remote processor message.

- Explicitly reenable ECC checking after a warm reset in Altera OCRAM as those
  registers are reset to default otherwise

- Fix single-bit error injection in Altera EDAC to not inject errors directly
  in ECC RAM and thus lead to false double-bit errors due to same ECC RAM
  being in concurrent use

----------------------------------------------------------------
Niravkumar L Rabara (2):
      EDAC/altera: Handle OCRAM ECC enable after warm reset
      EDAC/altera: Use INTTEST register for Ethernet and USB SBE injection

Shubhrajyoti Datta (1):
      EDAC/versalnet: Handle split messages for non-standard errors

 drivers/edac/altera_edac.c    | 22 +++++++++++++++++-----
 drivers/edac/versalnet_edac.c | 24 +++++++++++++-----------
 2 files changed, 30 insertions(+), 16 deletions(-)


-- 
Regards/Gruss,
    Boris.

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