Re: [PATCH v6 0/7] Introduce SpacemiT K1 PCIe phy and host controller

From: Alex Elder
Date: Mon Nov 17 2025 - 12:20:44 EST


On 11/14/25 10:21 PM, Jason Montleon wrote:
On Thu, Nov 13, 2025 at 4:45 PM Alex Elder <elder@xxxxxxxxxxxx> wrote:

This series introduces a PHY driver and a PCIe driver to support PCIe
on the SpacemiT K1 SoC. The PCIe implementation is derived from a
Synopsys DesignWare PCIe IP. The PHY driver supports one combination
PCIe/USB PHY as well as two PCIe-only PHYs. The combo PHY port uses
one PCIe lane, and the other two ports each have two lanes. All PCIe
ports operate at 5 GT/second.

The PCIe PHYs must be configured using a value that can only be
determined using the combo PHY, operating in PCIe mode. To allow
that PHY to be used for USB, the needed calibration step is performed
by the PHY driver automatically at probe time. Once this step is done,
the PHY can be used for either PCIe or USB.

The driver supports 256 MSIs, and initially does not support PCI INTx
interrupts. The hardware does not support MSI-X.

Version 6 of this series addresses a few comments from Christophe
Jaillet, and improves a workaround that disables ASPM L1. The two
people who had reported errors on earlier versions of this code have
confirmed their NVMe devices now work when configured with the default
RISC-V kernel configuration.

I successfully tested this patchset on a Banana Pi F3 and also a
Milk-V M1 Jupiter by making the same additions to k1-milkv-jupiter.dts
as were made to k1-bananapi-f3.dts.
I no longer have problems with NVME devices like I did when I tried v3 and v4.

Tested-by: Jason Montleon <jmontleo@xxxxxxxxxx>

Thank you very much for testing this. Your Tested-by is included
in Mani's commit.

-Alex