Re: [PATCH net-next v2 2/3] net: stmmac: Add glue driver for Motorcomm YT6801 ethernet controller

[Yao Zi]

On Sun, Nov 16, 2025 at 02:50:48PM +0800, Xi Ruoyao wrote:
> On Sat, 2025-11-15 at 11:46 +0000, Yao Zi wrote:
> > On Tue, Nov 11, 2025 at 12:32:56PM +0000, Russell King (Oracle) wrote:
> > > On Tue, Nov 11, 2025 at 10:52:51AM +0000, Yao Zi wrote:
> > > > +	plat->bus_id		= pci_dev_id(pdev);
> > > > +	plat->phy_addr		= -1;
> > > > +	plat->phy_interface	= PHY_INTERFACE_MODE_GMII;
> > > > +	plat->clk_csr		= STMMAC_CSR_20_35M;
> > > 
> > > Could you include a comment indicating what the stmmac clock rate
> > > actually is (the rate which is used to derive this divider) ? As
> > > this is PCI, I'm guessing it's 33MHz, which fits with your divider
> > > value.
> > 
> > The divider is taken from vendor driver, and the clock path isn't
> > mentioned in the datasheet, either. I don't think it's 33MHz since
> > it's
> > a PCIe chip, and there's no 33MHz clock supplied by PCIe.
> > 
> > The datasheet[1] (Chinese website, requires login) mentions that the
> > controller requires a 25MHz external clock input/oscillator to
> > function,
> > 
> > > 25MHz Crystal Input pin.
> > > 
> > > If use external oscillator or clock from another device.
> > >   1. When connect an external 25MHz oscillator or clock from another
> > >   device to XTAL_O pin, XTAL_I must be shorted to GND.
> > >   2. When connect an external 25MHz oscillator or clock from another
> > >   device to XTAL_I pin, keep the XTAL_O floating.
> > 
> > 25MHz fits in STMMAC_CSR_20_35M, too, so it's more likely the clock
> > source.
> > 
> > I don't think this guess could be confirmed without vendor's help,
> > should the information be included as comment.
> 
> I used the "beep" function of a multimeter to "probe" the connectivity
> of the two YT6801 chips on a XB612B0 V1.1 board.  There are two 25 MHz
> oscillators on the board, each connected to a YT6801.

Sorry for not being clear here, I'm sure the controller requires an
oscillators to function (since the datasheet states so). What's unclear
here is whether the 20~35MHz clock provided for internal MDIO bus is
dervided from it.

Anyway, I would add a comment to mention this in v3. Thanks.

Best regards,
Yao Zi

> -- 
> Xi Ruoyao <xry111@xxxxxxxxxxx>