[PATCH 2/4] clk: imx95-blk-ctl: fix hsio_blk_ctl_clk_dev_data reg offset

[Xu Yang]

The first item of hsio_blk_ctl_clk_dev_data is used to control PCIe
reference clock. The reg offset should be 0xc0 in HSIO block control
register map. Correct it so that other hsio block control items can
be added later. This will also rename the name to "hsio_pcie_clk_gate"
for better distinction.

Fixes: cf295252f0d8 ("clk: imx95-blk-ctl: Add one clock gate for HSIO block")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Xu Yang <xu.yang_2@xxxxxxx>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 56bed4471995..3c2019f428c9 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -285,10 +285,10 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
 
 static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
 	[0] = {
-		.name = "hsio_blk_ctl_clk",
+		.name = "hsio_pcie_clk_gate",
 		.parent_names = (const char *[]){ "hsio_pll", },
 		.num_parents = 1,
-		.reg = 0,
+		.reg = 0xc0,
 		.bit_idx = 6,
 		.bit_width = 1,
 		.type = CLK_GATE,
-- 
2.34.1