Re: [PATCH v11 0/7] Add support for DU/DSI clocks and DSI driver support for the Renesas RZ/V2H(P) SoC

[Lad, Prabhakar]

Hi Laurent,

On Tue, Nov 18, 2025 at 11:34 AM Laurent Pinchart
<laurent.pinchart@xxxxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Tue, Nov 18, 2025 at 11:21:12AM +0000, Lad, Prabhakar wrote:
> > On Mon, Oct 27, 2025 at 11:23 AM Geert Uytterhoeven wrote:
> > > On Tue, 21 Oct 2025 at 20:45, Laurent Pinchart wrote:
> > > > On Tue, Oct 21, 2025 at 07:26:49PM +0100, Lad, Prabhakar wrote:
> > > > > On Tue, Oct 21, 2025 at 11:26 AM Geert Uytterhoeven wrote:
> > > > > > On Wed, 15 Oct 2025 at 21:26, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > > > > > This patch series adds DU/DSI clocks and provides support for the
> > > > > > > MIPI DSI interface on the RZ/V2H(P) SoC.
> > > > > > >
> > > > > > > v10->v11:
> > > > > > > - Split CPG_PLL_CLK1_K/M/PDIV macro change into separate patch
> > > > > > > - Updated rzv2h_cpg_plldsi_div_determine_rate()
> > > > > > >   while iterating over the divider table
> > > > > > > - Added Acked-by tag from Tomi for patch 2/7 and 3/7
> > > > > > > - Added Reviewed-by tag from Geert for patch 2/7 and 3/7
> > > > > >
> > > > > > I think this series is ready for merging.
> > > > >
> > > > > \o/
> > > > >
> > > > > > > Lad Prabhakar (7):
> > > > > > >   clk: renesas: rzv2h-cpg: Add instance field to struct pll
> > > > > > >   clk: renesas: rzv2h-cpg: Use GENMASK for PLL fields
> > > > > > >   clk: renesas: rzv2h-cpg: Add support for DSI clocks
> > > > > > >   clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC
> > > > > > >   dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and
> > > > > > >     RZ/V2N
> > > > > > >   drm: renesas: rz-du: mipi_dsi: Add LPCLK clock support
> > > > > > >   drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC
> > > > > >
> > > > > > As this touches both clk and drm, let's discuss the merge strategy.
> > > > > > My proposal:
> > > > > >   1. I queue patches 1-3 in an immutable branch with a signed tag,
> > > > > >      to be used as a base for the remaining patches,
> > >
> > > Done:
> > >
> > > The following changes since commit 3a8660878839faadb4f1a6dd72c3179c1df56787:
> > >
> > >   Linux 6.18-rc1 (2025-10-12 13:42:36 -0700)
> > >
> > > are available in the Git repository at:
> > >
> > >   git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
> > > tags/clk-renesas-rzv2h-plldsi-tag
> > >
> > > for you to fetch changes up to f864e4b721e386be132cc973eadefe5d52cdfd94:
> > >
> > >   clk: renesas: rzv2h: Add support for DSI clocks (2025-10-27 11:58:03 +0100)
> > >
> > > ----------------------------------------------------------------
> > > clk: renesas: rzv2h: Add support for DSI clocks
> > >
> > > RZ/V2H Clock Pulse Generator PLLDSI API, shared by clock and MIPI DSI
> > > driver source files.
> > >
> > > ----------------------------------------------------------------
> > > Lad Prabhakar (3):
> > >       clk: renesas: rzv2h: Add instance field to struct pll
> > >       clk: renesas: rzv2h: Use GENMASK for PLL fields
> > >       clk: renesas: rzv2h: Add support for DSI clocks
> > >
> > >  drivers/clk/renesas/rzv2h-cpg.c | 512 +++++++++++++++++++++++++++++++++++++++-
> > >  drivers/clk/renesas/rzv2h-cpg.h |  26 +-
> > >  include/linux/clk/renesas.h     | 145 ++++++++++++
> > >  3 files changed, 672 insertions(+), 11 deletions(-)
> > >
> > > > > >   2. I queue patch 4 on top of 1 in renesas-clk for v6.19,
> > >
> > > Done.
> >
> > Can you please pick up the DSI patches.
>
> We can't, this has to be done by a drm-misc maintainer as it involves
> merging a non-fast forward branch instead of pushing commit directly on
> top of drm-misc-next.
>
I see, thank you. Talking to Geert we are closed for v6.19 as the
SoC+board changes have not made into v6.19. Probably we can wait for
the next cycle and Biju should be able to pick them up.

Cheers,
Prabhakar