RE: [PATCH v3 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 21 November 2025 16:29
> Subject: Re: [PATCH v3 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> 
> Hi Biju,
> 
> On Fri, 14 Nov 2025 at 11:52, Biju <biju.das.au@xxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Add documentation for the serial communication interface (RSCI) found
> > on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is
> > identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage
> > FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode
> > operation. RZ/G3E has 6 clocks(5 module clocks + 1 external clock)
> > compared to 3 clocks
> > (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
> >
> > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > @@ -10,17 +10,16 @@ maintainers:
> >    - Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> >    - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > -allOf:
> > -  - $ref: serial.yaml#
> > -
> >  properties:
> >    compatible:
> >      oneOf:
> > -      - items:
> > -          - const: renesas,r9a09g087-rsci # RZ/N2H
> > -          - const: renesas,r9a09g077-rsci # RZ/T2H
> > +      - enum:
> > +          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> > +          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
> 
> I can't find the non-FIFO ports in the documentation?
> Do you mean "Selectable to 1-stage register or 32-stage FIFO"?
> Isn't that software configuration instead of hardware description?

Basically, it has 2 modes. FIFO mode(CCR3.FM=1b) and Non-FIFO mode (CCR3.FM=0b).
DMAC can be used only in FIFO mode and there are some hardware differences
between two as FIFO reg block is applicable only for FIFO mode.

It has to be a dt property as based on the end user use case this IP needs 
to configured either in FIFO mode or non-FIFO mode from the boot.

It has to be either a compatible or a boolean property "renesas, rsci-non-fifo"
Or something else

What do you think? Please suggest.

> 
> > +          - renesas,r9a09g077-rsci # RZ/T2H
> >
> >        - items:
> > +          - const: renesas,r9a09g087-rsci # RZ/N2H
> >            - const: renesas,r9a09g077-rsci # RZ/T2H
> >
> >    reg:
> > @@ -42,14 +41,36 @@ properties:
> >
> >    clocks:
> >      minItems: 2
> > -    maxItems: 3
> > +    maxItems: 6
> >
> >    clock-names:
> > -    minItems: 2
> > +    oneOf:
> > +      - items:
> > +          - const: operation
> > +          - const: bus
> > +          - const: sck # optional external clock input
> > +
> > +        minItems: 2
> > +
> > +      - items:
> > +          - const: bus
> 
> Figure 7.3-1 ("RSCI Block Diagram") calls this "pclk".

OK.

> 
> > +          - const: tclk
> > +          - const: tclk_div64
> > +          - const: tclk_div16
> > +          - const: tclk_div4
> 
> Perhaps reverse the order of the last three, for simpler handling in the driver: each successive clock
> divides by four?  (yes, I know SCI_FCK is not immediately followed by SCI_FCK_DIV* in the driver)

OK, will reverse the order.

Cheers,
Biju