[PATCH v5] pwm: rzg2l-gpt: Reinitialize the cache value in rzg2l_gpt_disable()

[Biju]

From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

The rzg2l_gpt_config() test the rzg2l_gpt->period_tick variable. This
check is not valid, if enabling of a channel happens after disabling all
the channels as it test against the cached value. Therefore, reinitialize
the variable rzg2l_gpt->period_tick to 0 in rzg2l_gpt_disable(), when
all the logical channels of a hardware channel is disabled, and also don't
allow to set the cached value in rzg2l_gpt_config(), if the other channel
is not enabled.

Cc: stable@xxxxxxxxxx
Fixes: 061f087f5d0b ("pwm: Add support for RZ/G2L GPT")
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v4->v5:
 * Updated commit description and code comment to give more details on why
   reinitialising the cached value to zero
 * Added a check in rzg2l_gpt_config(), to prevent setting the cached value, if
   the other channel is not enabled.
v3->v4:
 * Split the patch as separate from [1] for easy merging.
 * Updated commit description
 * Added comments about the fix in rzg2l_gpt_disable()
v3:
 * New patch

[1] https://lore.kernel.org/all/20250915163637.3572-1-biju.das.jz@xxxxxxxxxxxxxx/#t
---
 drivers/pwm/pwm-rzg2l-gpt.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 360c8bf3b190..38ad03ded9ce 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -190,8 +190,17 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
 	/* Stop count, Output low on GTIOCx pin when counting stops */
 	rzg2l_gpt->channel_enable_count[ch]--;
 
-	if (!rzg2l_gpt->channel_enable_count[ch])
+	if (!rzg2l_gpt->channel_enable_count[ch]) {
 		rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_CST, 0);
+		/*
+		 * The rzg2l_gpt_config() test the rzg2l_gpt->period_tick
+		 * variable. This check is not valid, if enabling of a channel
+		 * happens after disabling all the channels as it test against
+		 * the cached value. Therefore, reinitialize the variable
+		 * rzg2l_gpt->period_tick to 0.
+		 */
+		rzg2l_gpt->period_ticks[ch] = 0;
+	}
 
 	/* Disable pin output */
 	rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(ch), RZG2L_GTIOR_OxE(sub_ch), 0);
@@ -271,10 +280,14 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	 * in use with different settings.
 	 */
 	if (rzg2l_gpt->channel_request_count[ch] > 1) {
-		if (period_ticks < rzg2l_gpt->period_ticks[ch])
-			return -EBUSY;
-		else
-			period_ticks = rzg2l_gpt->period_ticks[ch];
+		u8 other_sub_ch = sub_ch ? (pwm->hwpwm - 1) : (pwm->hwpwm + 1);
+
+		if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, other_sub_ch)) {
+			if (period_ticks < rzg2l_gpt->period_ticks[ch])
+				return -EBUSY;
+			else
+				period_ticks = rzg2l_gpt->period_ticks[ch];
+		}
 	}
 
 	prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
-- 
2.43.0