Re: [PATCH v6 1/2] dt-bindings: fpga: stratix10: add support for Agilex5

[Conor Dooley]

On Wed, Nov 19, 2025 at 10:26:05AM +0800, Khairul Anuar Romli wrote:
> Agilex5 introduces changes in how reserved memory is mapped and accessed
> compared to previous SoC generations. Agilex5 compatible allows stratix10-
> FPGA manager driver to handle these changes.
> 
> Fallback is added for driver probe and init that rely on matching of table
> and DT node.
> 
> Reviewed-by: Xu Yilun <yilun.xu@xxxxxxxxx>
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@xxxxxxxxxx>


Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
pw-bot: not-applicable

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