Re: [PATCH 21/24] arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes

From: Manaf Meethalavalappu Pallikunhi

Date: Wed Nov 19 2025 - 08:10:38 EST

Hi Konrad,


On 9/25/2025 4:45 PM, Konrad Dybcio wrote:
On 9/25/25 8:32 AM, Pankaj Patil wrote:
From: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@xxxxxxxxxxxxxxxx>

Add tsens and thermal zones nodes for Glymur SoC.

Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@xxxxxxxxxxxxxxxx>
Signed-off-by: Pankaj Patil <pankaj.patil@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 1998 ++++++++++++++++++++++++++++++++++
1 file changed, 1998 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 17a07d33b9396dba00e61a3b4260fa1a535600f2..986dc385200029071136068ab79ff8dd66d5284a 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2790,6 +2790,134 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ tsens0: thermal-sensor@c22c000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22c000 0 0x1000>, /* TM */
+ <0 0x0c222000 0 0x1000>; /* SROT */
These comments are not useful

I noticed that some patches use reg = <0x0, while others use reg = <0

please unify them for the former
I will update in next revision

+
+ interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
pdc 26
We don't have any usecase to enable it as pdc interrupt and don't want to wake up from sleep as it is already in lowest power mode.

+ <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c22d000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22d000 0 0x1000>, /* TM */
+ <0 0x0c223000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
pdc 27

+ <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <9>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens2: thermal-sensor@c22e000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22e000 0 0x1000>, /* TM */
+ <0 0x0c224000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
pdc 28

+ <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens3: thermal-sensor@c22f000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22f000 0 0x1000>, /* TM */
+ <0 0x0c225000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
pdc 29

+ <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <8>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens4: thermal-sensor@c230000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c230000 0 0x1000>, /* TM */
+ <0 0x0c226000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
pdc 46

+ <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens5: thermal-sensor@c231000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c231000 0 0x1000>, /* TM */
+ <0 0x0c227000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>,
pdc 108

+ <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <8>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens6: thermal-sensor@c232000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c232000 0 0x1000>, /* TM */
+ <0 0x0c228000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>,
pdc 109

+ <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens7: thermal-sensor@c233000 {
+ compatible = "qcom,glymur-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c233000 0 0x1000>, /* TM */
+ <0 0x0c229000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>,
pdc 110

+ <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <15>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
aoss_qmp: power-management@c300000 {
compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>;
@@ -4611,4 +4739,1874 @@ timer {
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+
+ thermal_zones: thermal-zones {
+ aoss-0-thermal {
+ thermal-sensors = <&tsens0 0>;
You need one more \t here

+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+ aoss-0-critical {
Please keep a \n between subnodes and between the last property and
following subnodes
I will update in next revision


+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
See:

06eadce93697 ("arm64: dts: qcom: x1e80100: Drop unused passive thermal trip points for CPU")

It also only makes sense to keep "hot" trips for devices where we
can actually apply some cooling (e.g. the GPU)

I will update in next revision

Thank you

Manaf


Konrad