Re: [PATCH v6 0/2] genirq: s390/pci: Migrate MSI interrupts to irqdomain API

[Tobias Schumacher]

On Mon Nov 24, 2025 at 11:30 AM CET, Gerd Bayer wrote:
> On Fri, 2025-11-21 at 16:45 +0100, Tobias Schumacher wrote:
>> This patch series reworks the PCIe interrupt handling on s390 by
>> migrating it to use a proper MSI parent domain. Introducing a dedicated
>> MSI domain hierarchy aligns s390 PCIe support with the generic Linux IRQ
>> domain model. Currently s390 is one of the last architectures still using
>> the legacy API.
>> 
>> The migration splits the existing code in the legacy functions
>> arch_setup_msi_irqs() and arch_teardown_msi_irqs() into different
>> callbacks of the newly created MSI parent domain:
>> 
>> - zpci_msi_prepare(): prepare the allocation of per-device MSI IRQs.
>>       will be called once for each device before allocating individual
>>       IRQs and sets up for example the adapter aisb and aibv.
>> - zpci_msi_teardown(): reverts the effects of zpci_msi_prepare() and is
>>       called after all MSI IRQs are freed.
>> - zpci_msi_domain_alloc(): the allocation function for interrupts
>> - zpci_msi_domain_free(): revert the effects of zpci_msi_domain_alloc()
>> - zpci_compose_msi_msg(): create the MSI message to be written into the
>>       corresponding PCI config space.
>> 
>> * Patch 1 fixes an inconsistency in the irqdomain API. Internally, hw
>>   irqs are represented by an unsigned long int (irq_hw_number_t) while
>>   the external API in some cases takes an unsigned int as parameter.
>>   This fix was required in V2 of the patchset. Due to conceptual changes
>>   in patch 2 it is not required anymore for s390, but still seems
>>   sensible.
>> * Patch 2 implements IRQ domains for s390 PCI
>> 
>> Since patch 1 changes common APIs, some build tests were done for x86_64
>> and arm64. 
>> 
>
> I just ran some error inject test on mxl5_core on a z15 zVM system with
> `zpcictl --reset-fw <PCI-ID>`
>
> With your patch series PCI autorecovery does not finish, unfortunately.
> Instead HW presents an Event 0x10 (MSI was received from the PCI
> function, while no AIRQ was registered)
>
> I'm afraid, there might be more work required...
> Gerd

Thanks, I'll have a look.

Tobias