Re: [PATCH v3 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Geert Uytterhoeven]

Hi Biju,

On Sat, 22 Nov 2025 at 15:15, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> > > On Fri, 14 Nov 2025 at 11:52, Biju <biju.das.au@xxxxxxxxx> wrote:
> > > > Add documentation for the serial communication interface (RSCI)
> > > > found on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC
> > > > is identical to that on the RZ/T2H (R9A09G077) SoC, but it has a
> > > > 32-stage FIFO compared to 16 on RZ/T2H. It supports both FIFO and
> > > > non-FIFO mode operation. RZ/G3E has 6 clocks(5 module clocks + 1
> > > > external clock) compared to 3 clocks
> > > > (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
> > > >
> > > > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

> > > > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > > > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > > > @@ -10,17 +10,16 @@ maintainers:
> > > >    - Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> > > >    - Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > >
> > > > -allOf:
> > > > -  - $ref: serial.yaml#
> > > > -
> > > >  properties:
> > > >    compatible:
> > > >      oneOf:
> > > > -      - items:
> > > > -          - const: renesas,r9a09g087-rsci # RZ/N2H
> > > > -          - const: renesas,r9a09g077-rsci # RZ/T2H
> > > > +      - enum:
> > > > +          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> > > > +          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
> > >
> > > I can't find the non-FIFO ports in the documentation?
> > > Do you mean "Selectable to 1-stage register or 32-stage FIFO"?
> > > Isn't that software configuration instead of hardware description?
> >
> > Basically, it has 2 modes. FIFO mode(CCR3.FM=1b) and Non-FIFO mode (CCR3.FM=0b).
> > DMAC can be used only in FIFO mode and there are some hardware differences between two as FIFO reg
> > block is applicable only for FIFO mode.

Still, sounds like software policy / configuration to me...

> > It has to be either a compatible or a boolean property "renesas, rsci-non-fifo"
> > Or something else
>
> I believe it must be a compatible to support non-FIFO mode from boot.
>
> I maybe wrong. Please correct me, if it I am wrong.

Why can't it be configured through e.g. the rx_fifo_trigger device
attribute, or some setserial option? Any guidance from the serial
experts?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds