Re: [PATCH] clk: renesas: r9a09g077: Propagate rate changes through mux parents

[Geert Uytterhoeven]

On Fri, 21 Nov 2025 at 10:09, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Enable CLK_SET_RATE_PARENT for mux clocks so that rate changes can properly
> propagate to their parent clocks. Several clocks in the R9A09G077 CPG tree
> depend on upstream PLL or divider outputs being recalculated when a child
> requests a new frequency. Without this flag, rate adjustments stop at the
> mux layer, leaving parent rates unchanged and preventing the clock tree
> from converging on the intended values.
>
> Set the flag in DEF_MUX to ensure that parent clocks participate in rate
> negotiation, which is required for correct operation of the display and
> peripheral related clocks being added for RZ/T2H support.
>
> Fixes: 065fe720eec6e ("clk: renesas: Add support for R9A09G077 SoC")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.20.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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