Re: [PATCH 0/4 v6] PCI: s32g: Add support for PCIe controller

[Manivannan Sadhasivam]

On Fri, 21 Nov 2025 17:49:16 +0100, Vincent Guittot wrote:
> The S32G SoC family has 2 PCIe controllers based on Designware IP.
> 
> Add the support for Host mode.
> 
> Change since v5:
> 
> - Removed relocatable bit in yaml
> - Dropped pcie-nxp-s32g-regs.h and moved reg definition in pcie-nxp-s32g.c
> - Removed a useless ret
> - Change kconfig from tri to bool because of memblock_start_of_DRAM()
> 
> [...]

Applied, thanks!

[1/4] dt-bindings: PCI: s32g: Add NXP PCIe controller
      commit: dd17ec3df57b7bd0d23f3a17124d59b2740d81e4
[2/4] PCI: dw: Add more registers and bitfield definition
      commit: bd1be33651b21ce15eee8fa2f080109e3eaa8e29
[3/4] PCI: s32g: Add initial PCIe support (RC)
      commit: c403d6d7282b72fe1a0812c99beeeefb1a7e1f4b
[4/4] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver
      commit: 58fc675c34c583771d412aa89fb364c750fadacf

Best regards,
-- 
Manivannan Sadhasivam <mani@xxxxxxxxxx>