Re: [PATCH v8 4/6] arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock

[Manivannan Sadhasivam]

On Wed, Nov 19, 2025 at 04:35:21PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> 
> Versa3 clock generator available on RZ/G3S SMARC Module provides the
> reference clock for SoC PCIe interface. Update the device tree to reflect
> this connection.
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>

Acked-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>

- Mani

> ---
> 
> Changes in v8:
> - none
> 
> Changes in v7:
> - none
> 
> Changes in v6:
> - collected tags
> 
> Changes in v5:
> - this patch is the result of dropping the updates to dma-ranges for
>   secure area and keeping only the remaining bits
> 
>  arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> index 39845faec894..b196f57fd551 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -172,6 +172,11 @@ a0 80 30 30 9c
>  	};
>  };
>  
> +&pcie_port0 {
> +	clocks = <&versa3 5>;
> +	clock-names = "ref";
> +};
> +
>  #if SW_CONFIG2 == SW_ON
>  /* SD0 slot */
>  &sdhi0 {
> -- 
> 2.43.0
> 

-- 
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