RE: [PATCH v2 08/10] dt-bindings: connector: Add PCIe M.2 Mechanical Key E connector

From: Sherry Sun
Date: Tue Nov 25 2025 - 21:39:16 EST

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> -----Original Message-----
> From: Manivannan Sadhasivam via B4 Relay
> <devnull+manivannan.sadhasivam.oss.qualcomm.com@xxxxxxxxxx>
> Sent: Tuesday, November 25, 2025 10:45 PM
> To: Rob Herring <robh@xxxxxxxxxx>; Greg Kroah-Hartman
> <gregkh@xxxxxxxxxxxxxxxxxxx>; Jiri Slaby <jirislaby@xxxxxxxxxx>; Nathan
> Chancellor <nathan@xxxxxxxxxx>; Nicolas Schier <nicolas.schier@xxxxxxxxx>;
> Hans de Goede <hansg@xxxxxxxxxx>; Ilpo Järvinen
> <ilpo.jarvinen@xxxxxxxxxxxxxxx>; Mark Pearson <mpearson-
> lenovo@xxxxxxxxx>; Derek J. Clark <derekjohn.clark@xxxxxxxxx>;
> Manivannan Sadhasivam <mani@xxxxxxxxxx>; Krzysztof Kozlowski
> <krzk+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>; Marcel
> Holtmann <marcel@xxxxxxxxxxxx>; Luiz Augusto von Dentz
> <luiz.dentz@xxxxxxxxx>; Bartosz Golaszewski <brgl@xxxxxxxx>
> Cc: linux-serial@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-
> kbuild@xxxxxxxxxxxxxxx; platform-driver-x86@xxxxxxxxxxxxxxx; linux-
> pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-arm-
> msm@xxxxxxxxxxxxxxx; linux-bluetooth@xxxxxxxxxxxxxxx; linux-
> pm@xxxxxxxxxxxxxxx; Stephan Gerhold <stephan.gerhold@xxxxxxxxxx>; Dmitry
> Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>; Manivannan
> Sadhasivam <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
> Subject: [PATCH v2 08/10] dt-bindings: connector: Add PCIe M.2 Mechanical
> Key E connector
>
> From: Manivannan Sadhasivam
> <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
>
> Add the devicetree binding for PCIe M.2 Mechanical Key E connector defined
> in the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector provides
> interfaces like PCIe or SDIO to attach the WiFi devices to the host machine,
> USB or UART+PCM interfaces to attach the Bluetooth (BT) devices along with
> additional interfaces like I2C for NFC solution. At any point of time, the
> connector can only support either PCIe or SDIO as the WiFi interface and USB
> or UART as the BT interface.
>
> The connector provides a primary power supply of 3.3v, along with an
> optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at 1.8v
> sideband signaling.
>
> The connector also supplies optional signals in the form of GPIOs for fine
> grained power management.
>
> Signed-off-by: Manivannan Sadhasivam
> <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
> ---
> .../bindings/connector/pcie-m2-e-connector.yaml | 178
> +++++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 179 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-
> connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-
> connector.yaml
> new file mode 100644
> index 000000000000..fe2c9a943a21
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-
> connector.ya
> +++ ml
> @@ -0,0 +1,178 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---
> +$id:
> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevice
> +tree.org%2Fschemas%2Fconnector%2Fpcie-m2-e-
> connector.yaml%23&data=05%7C
> +02%7Csherry.sun%40nxp.com%7C22ea3ba76ac749b69bee08de2c314c73%7
> C686ea1d3
> +bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638996787414741474%7CUnkno
> wn%7CTWFpb
> +GZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4z
> MiIsIkFO
> +IjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=Y8y5ctS7QJzaMZ
> wdY%2FAnr
> +FqydRTUumh3hRBDMtK%2B8Y4%3D&reserved=0
> +$schema:
> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevice
> +tree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=05%7C02%7Csherry.sun%40nxp.
> +com%7C22ea3ba76ac749b69bee08de2c314c73%7C686ea1d3bc2b4c6fa92cd
> 99c5c3016
> +35%7C0%7C0%7C638996787414756341%7CUnknown%7CTWFpbGZsb3d8ey
> JFbXB0eU1hcGk
> +iOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIj
> oyfQ
> +%3D%3D%7C0%7C%7C%7C&sdata=z9JeuCv1%2BkOH%2FjQcV2hpwgfuMJykj
> 1SFgn4EzkHSK
> +0Q%3D&reserved=0
> +
> +title: PCIe M.2 Mechanical Key E Connector
> +
> +maintainers:
> + - Manivannan Sadhasivam
> <manivannan.sadhasivam@xxxxxxxxxxxxxxxx>
> +
> +description:
> + A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical
> +Key E
> + connector. Mechanical Key E connectors are used to connect Wireless
> + Connectivity devices including combinations of Wi-Fi, BT, NFC to the
> +host
> + machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C.
> +
> +properties:
> + compatible:
> + const: pcie-m2-e-connector
> +
> + vpcie3v3-supply:
> + description: A phandle to the regulator for 3.3v supply.
> +
> + vpcie1v8-supply:
> + description: A phandle to the regulator for VIO 1.8v supply.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> + description: OF graph bindings modeling the interfaces exposed on the
> + connector. Since a single connector can have multiple interfaces, every
> + interface has an assigned OF graph port number as described below.
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Connector interfaces for Wi-Fi
> +
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: PCIe interface
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: SDIO interface
> +
> + anyOf:
> + - required:
> + - endpoint@0
> + - required:
> + - endpoint@1
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Connector interfaces for BT
> +
> + properties:
> + endpoint@0:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: USB 2.0 interface
> +
> + endpoint@1:
> + $ref: /schemas/graph.yaml#/properties/endpoint
> + description: UART interface
> +
> + anyOf:
> + - required:
> + - endpoint@0
> + - required:
> + - endpoint@1
> +
> + port@2:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: PCM/I2S interface
> +
> + port@3:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: I2C interface
> +
> + oneOf:
> + - required:
> + - port@0
> +
> + clocks:
> + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host
> system to
> + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
> + more details.
> + maxItems: 1
> +
> + w-disable1-gpios:
> + description: GPIO controlled connection to W_DISABLE1# signal. This
> signal
> + is used by the system to disable WiFi radio in the M.2 card. Refer, PCI
> + Express M.2 Specification r4.0, sec 3.1.12.3 for more details.
> + maxItems: 1
> +
> + w-disable2-gpios:
> + description: GPIO controlled connection to W_DISABLE2# signal. This
> signal
> + is used by the system to disable BT radio in the M.2 card. Refer, PCI
> + Express M.2 Specification r4.0, sec 3.1.12.3 for more details.
> + maxItems: 1
> +
> + viocfg-gpios:
> + description: GPIO controlled connection to IO voltage configuration
> + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the
> + host system that the card supports an independent IO voltage domain for
> + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec
> + 3.1.15.1 for more details.
> + maxItems: 1
> +
> + uim-power-src-gpios:
> + description: GPIO controlled connection to UIM_POWER_SRC signal. This
> signal
> + is used when the NFC solution is implemented and receives the power
> output
> + from WWAN_UIM_PWR signal of the another WWAN M.2 card. Refer,
> PCI Express
> + M.2 Specification r4.0, sec 3.1.11.1 for more details.
> + maxItems: 1
> +
> + uim-power-snk-gpios:
> + description: GPIO controlled connection to UIM_POWER_SNK signal. This
> signal
> + is used when the NFC solution is implemented and supplies power to the
> + Universal Integrated Circuit Card (UICC). Refer, PCI Express M.2
> + Specification r4.0, sec 3.1.11.2 for more details.
> + maxItems: 1
> +
> + uim-swp-gpios:
> + description: GPIO controlled connection to UIM_SWP signal. This signal is
> + used when the NFC solution is implemented and implements the Single
> Wire
> + Protocol (SWP) interface to the UICC. Refer, PCI Express M.2 Specification
> + r4.0, sec 3.1.11.3 for more details.
> + maxItems: 1
> +
> +required:
> + - compatible
> + - vpcie3v3-supply

Hi Mani,

I am wondering if vpcie3v3-supply property is necessary here, consider the following real board designs on our i.MX platforms.

1. M.2 power always on, it connected to board VDD_3V3, no control gpio. Should we not configure the vpcie3v3-supply or add the fake regulator like the one below?
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = " M.2-power";
};

2. M.2 power regulator reuses w_disable1# gpio for control. Should we use the vpcie3v3-supply or w-disable1-gpios to control this?

Best Regards
Sherry

Next message: Jakub Kicinski: "Re: [PATCH net-next 1/1] net: mdio: reset PHY before attempting to access ID register"
Previous message: jiefeng . z . zhang: "[PATCH net v4] net: atlantic: fix fragment overflow handling in RX path"
In reply to: Frank Li: "Re: [PATCH v2 08/10] dt-bindings: connector: Add PCIe M.2 Mechanical Key E connector"
Next in thread: Manivannan Sadhasivam via B4 Relay: "[PATCH v2 09/10] Bluetooth: hci_qca: Add support for WCN7850 PCIe M.2 card"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]