Re: [RFC PATCH] iommu/amd: Add control register in `struct iommu_hw_info_amd`

[Sairaj Kodilkar]

On 11/22/2025 5:05 AM, Jason Gunthorpe wrote:
> On Wed, Oct 29, 2025 at 03:28:46PM +0530, Sairaj Kodilkar wrote:
> > When user does IOMMU_GET_HW_INFO ioctl, read the IOMMU control
> > register (MMIO offset 0x0018) and return it as part of
> > `struct iommu_hw_info_amd`.
> >
> > Userspace can use this information to determine the features
> > supported by the underlying host kernel.
> >
> > Signed-off-by: Sairaj Kodilkar <sarunkod@xxxxxxx>
> > ---
> >
> > The patch exposes the control register to the user space so that QEMU
> > can determine the list of features enabled by the host IOMMU driver
> > when there are passthrough devices. QEMU can use this information to
> > selectively enable the guest feature. One example of such feature is
> > enabling upto 2048 MSIs for passthrough devices. QEMU must not enable
> > this feature for passthrough devices when host IOMMU driver has not
> > enabled it.
> Please document in the uapi header what bits are meaningful and
> userspace can safely access..
>
> You are OK that a 0 register means the kernel is old?

Yes. That's fine.
Please see 
https://lore.kernel.org/qemu-devel/20251118101532.4315-1-sarunkod@xxxxxxx/
Here qemu uses the control register only to determine the 2K interrupt 
support and sets
corrosponding bits inside the virtual control register. Other bits in 
the virtual control
register are predefined and do not change even if the hardware control 
register is
returned as 0.

Thanks
Sairaj