Re: [PATCH 09/22] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/G3E SoC

[Krzysztof Kozlowski]

On 26/11/2025 15:07, Tommaso Merciai wrote:
> The MIPI DSI interface on the RZ/G3E SoC is nearly identical to that of
> the RZ/V2H(P) SoC, except that this have 2 input port and can use vclk1
> or vclk2 as DSI Video clock, depending on the selected port.
> 
> To accommodate these differences, a SoC-specific
> `renesas,r9a09g047-mipi-dsi` compatible string has been added for the
> RZ/G3E SoC.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
> ---
>  .../bindings/display/bridge/renesas,dsi.yaml  | 120 +++++++++++++++---
>  1 file changed, 101 insertions(+), 19 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> index c20625b8425e..9917b494a9c9 100644
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> @@ -28,6 +28,7 @@ properties:
>            - const: renesas,r9a09g057-mipi-dsi
>  
>        - enum:
> +          - renesas,r9a09g047-mipi-dsi # RZ/G3E
>            - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
>  
>    reg:
> @@ -84,6 +85,13 @@ properties:
>            - const: pclk
>            - const: vclk
>            - const: lpclk
> +      - items:
> +          - const: pllrefclk
> +          - const: aclk
> +          - const: pclk
> +          - const: vclk1
> +          - const: vclk2
> +          - const: lpclk

Why are you creating completely new lists every time?

No, come with unified approach.

Best regards,
Krzysztof