Re: [PATCH v9 4/4] PCI: dwc: Support ECAM mechanism by enabling iATU 'CFG Shift Feature'

[Krishna Chaitanya Chundru]

On 11/28/2025 10:46 PM, Maciej W. Rozycki wrote:
> On Fri, 28 Nov 2025, Krishna Chaitanya Chundru wrote:
>
> > >    I have no slightest idea why it should cause a regression such as this,
> > > it seems totally unrelated.  Yet it's 100% reproducible.  Could this be
> > > because it's the only device in the system that actually uses PCI/e port
> > > I/O?
> > Hi Maciej, Can you try attached patch and let me know if that is helping you
> > or not. - Krishna Chaitanya.
>   No change, it's still broken, sorry.
HI Maciej,
For the previous patch can you apply this diff and share me dmesg o/p
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -448,7 +448,6 @@ static int dw_pcie_config_ecam_iatu(struct 
dw_pcie_rp *pp)
        if (ret)
                return ret;

-
        bus_range_max = resource_size(bus->res);

        if (bus_range_max < 2)
@@ -456,6 +455,8 @@ static int dw_pcie_config_ecam_iatu(struct 
dw_pcie_rp *pp)

        pp->ob_atu_index++;

+       dev_err(pci->dev, "Current iATU OB index %d\n", pp->ob_atu_index);
+
        /* Configure remaining buses in type 1 iATU configuration */
        atu.index = pp->ob_atu_index;
        atu.type = PCIE_ATU_TYPE_CFG1;
@@ -931,6 +932,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
                }
        }

+       dev_err(pci->dev, "Current iATU OB index %d\n", i);
        if (pp->io_size) {
                if (pci->num_ob_windows > ++i) {
                        atu.index = i;
@@ -946,6 +948,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
                                return ret;
                        }
                } else {
+                       dev_err(pci->dev, "Using shared io index %d\n", i);
                        pp->cfg0_io_shared = true;
                }
        }

- Krishna Chaitanya.
>    Maciej