Re: [PATCH v2 2/6] spi: microchip-core: Refactor FIFO read and write handlers

[Andy Shevchenko]

On Thu, Nov 27, 2025 at 06:05:04PM +0000, Conor Dooley wrote:
> On Thu, Nov 27, 2025 at 06:49:27PM +0200, Andy Shevchenko wrote:
> > On Thu, Nov 27, 2025 at 04:08:25PM +0000, Prajna Rajendra Kumar wrote:
> > > On 26/11/2025 12:13, Andy Shevchenko wrote:
> > > > On Wed, Nov 26, 2025 at 12:05:22PM +0000, Mark Brown wrote:
> > > > > On Wed, Nov 26, 2025 at 09:21:45AM +0000, david laight wrote:

...

> > > > > > I'm not sure I don't prefer the version with one writeb() call.
> > > > > > How about:
> > > > > >              writeb(spi->tx_buf ? *spi->tx_buf++ : 0xaa,
> > > > > >                      spi->regs + MCHP_CORESPI_REG_TXDATA);
> > > > > Please don't abuse the ternery operator like this, just write normal
> > > > > conditional statements.
> > > > FWIW, that's what my patch does already :-)
> > > 
> > > Thanks for the series. However, this particular patch appears to
> > > introduce a regression. The SPI controller reads an incorrect
> > > Device ID from the peripheral.
> > 
> > Hmm... This is interesting. The only thing I see is missed dummy byte read in
> > case of TX only transfers. Is this what you have?
> 
> Seems very likely, the hardware is pretty simple, so it has no concept
> of whether bytes it receives are useful or any ability to operate on
> transfers and discard data from the FIFOs when a new one starts. That's
> why the unconditional read is there to make sure the rx FIFO is kept in
> sync.

I have just sent a v3, please, give it a try.

-- 
With Best Regards,
Andy Shevchenko