Re: [PATCH v3 2/7] spi: Support controllers with multiple data lanes

[Andy Shevchenko]

On Mon, Dec 01, 2025 at 08:20:40PM -0600, David Lechner wrote:
> Add support for SPI controllers with multiple physical SPI data lanes.
> (A data lane in this context means lines connected to a serializer, so a
> controller with two data lanes would have two serializers in a single
> controller).

I'm a bit confused. Does it mean the three data lanes require three
serializers?

> This is common in the type of controller that can be used with parallel
> flash memories, but can be used for general purpose SPI as well.
> 
> To indicate support, a controller just needs to set ctlr->num_data_lanes
> to something greater than 1. Peripherals indicate which lane they are
> connected to via device tree (ACPI support can be added if needed).

...

> +	rc = of_property_read_variable_u32_array(nc, "data-lanes", lanes, 1,
> +						 ARRAY_SIZE(lanes));
> +	if (rc < 0 && rc != -EINVAL) {

It's a dup check for EINVAL, see below...

> +		dev_err(&ctlr->dev, "%pOF has invalid 'data-lanes' property (%d)\n",
> +			nc, rc);
> +		return rc;
> +	}
> +
> +	if (rc == -EINVAL) {
> +		/* Default when property is omitted. */
> +		spi->num_data_lanes = 1;


...just move it here as

	} else if (rc < 0) {
		...

(and yes, I know that this is not so usual pattern, but it makes the code less
 duplicative).

> +	} else {
> +		for (idx = 0; idx < rc; idx++) {
> +			if (lanes[idx] >= ctlr->num_data_lanes) {
> +				dev_err(&ctlr->dev,
> +					"%pOF has out of range 'data-lanes' property (%d/%d)\n",
> +					nc, lanes[idx], ctlr->num_data_lanes);
> +				return -EINVAL;
> +			}
> +			spi->data_lanes[idx] = lanes[idx];
> +		}
> +
> +		spi->num_data_lanes = rc;
> +	}

...

>   * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
>   *	the corresponding physical CS for logical CS i.
>   * @num_chipselect: Number of physical chipselects used.
> + * @data_lanes: Array of physical data lanes. This is only used with specialized
> + * controllers that support multiple data lanes.
> + * @num_data_lanes: Number of physical data lanes used.

This split the group of cs related members. Can you move it out or explain how
does it relate?

>   * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array
>   * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines
>   *	(optional, NULL when not using a GPIO line)

-- 
With Best Regards,
Andy Shevchenko