Re: [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init

[David Heidelberg]

On 05/12/2025 10:54, Konrad Dybcio wrote:
> On 12/4/25 5:32 PM, David Heidelberg via B4 Relay wrote:
> > From: Casey Connolly <casey.connolly@xxxxxxxxxx>
> >
> > Add a PHY configuration sequence for the sdm845 which uses a Qualcomm
> > Gen 2 version 1.1 CSI-2 PHY.
> >
> > The PHY can be configured as two phase or three phase in C-PHY or D-PHY
> > mode. This configuration supports three-phase C-PHY mode.
> >
> > Signed-off-by: Casey Connolly <casey.connolly@xxxxxxxxxx>
> > Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx>
> > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
> > Co-developed-by: David Heidelberg <david@xxxxxxx>
> > Signed-off-by: David Heidelberg <david@xxxxxxx>
> > ---
> >   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 74 +++++++++++++++++++++-
> >   1 file changed, 72 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> > index 3d30cdce33f96..7121aa97a19c4 100644
> > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> > @@ -145,6 +145,7 @@ csiphy_lane_regs lane_regs_sa8775p[] = {
> >   };
> >   
> >   /* GEN2 1.0 2PH */
> > +/* 5 entries: clock + 4 lanes */
> >   static const struct
> >   csiphy_lane_regs lane_regs_sdm845[] = {
> >   	{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> > @@ -219,6 +220,69 @@ csiphy_lane_regs lane_regs_sdm845[] = {
> >   	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> >   };
> >   
> > +/* GEN2 1.0 3PH */
> > +/* 3 entries: 3 lanes (C-PHY) */
> > +static const struct
> > +csiphy_lane_regs lane_regs_sdm845_3ph[] = {
>
> Here's a downstream snippet which seems to have more up-to-date settings
> (checked against a doc and it seems to have changes made at the time of
> the last edit of the doc)
>
> You'll notice it's split into 3 arrays of register sets - that's because
> it applies setting for each lane.. something to keep in mind we could
> optimize upstream data storage for (they are identical per lane in this
> instance) one day

see 87c2c2716523 ("media: qcom: camss: csiphy-3ph: Remove redundant PHY 
init sequence control loop")

for the reason to flatten the regs array (thou outside the scope of this 
patchset).

Regarding to the different value, I can test them, can you point to docs 
regarding why these regs has been changed and what the values means?

I thought it's some default seq, but as you show there is multiple 
versions, it make sense to properly document what these regs do.

David
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