Re: [PATCH v2 1/4] dt-bindings: interrupt-controller: document RZ/{T2H,N2H} ICU

[Rob Herring (Arm)]

On Mon, 01 Dec 2025 13:29:30 +0200, Cosmin Tanislav wrote:
> The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have
> an Interrupt Controller (ICU) block that routes external interrupts to
> the GIC's SPIs, with the ability of level-translation, and can also
> produce software interrupts and aggregate error interrupts.
> 
> It has 16 software triggered interrupts (INTCPUn), 16 external pin
> interrupts (IRQn), a System error interrupt (SEI), two Cortex-A55 error
> interrupts (CA55_ERRn), two Cortex-R52 error interrupts for each of the
> two cores (CR52x_ERRn), two Peripheral error interrupts (PERI_ERRn),
> two DSMIF error interrupts (DSMIF_ERRn), and two ENCIF error interrupts
> (ENCIF_ERRn).
> 
> The IRQn and SEI interrupts are exposed externally, while the others
> are software triggered.
> 
> INTCPU0 to INTCPU13, IRQ 0 to IRQ13 are non-safety interrupts, while
> INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are
> exposed via a separate register space.
> 
> Document them, and use RZ/T2H as a fallback for RZ/N2H as the ICU is
> entirely compatible.
> 
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@xxxxxxxxxxx>
> ---
> 
> V2:
>  * move reg property after compatible
> 
>  .../renesas,r9a09g077-icu.yaml                | 236 ++++++++++++++++++
>  1 file changed, 236 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>