Re: [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider

[Jie Luo]

On 12/1/2025 9:42 PM, Konrad Dybcio wrote:
> On 11/28/25 3:29 PM, Jie Luo wrote:
>>
>>
>> On 11/28/2025 7:38 PM, Konrad Dybcio wrote:
>>> On 11/28/25 9:40 AM, Luo Jie wrote:
>>>> The clk_cmn_pll_recalc_rate() function must account for the reference clock
>>>> divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
>>>> with a reference divider other than 1 calculate incorrect CMN PLL rates.
>>>> For example, on IPQ5332 where the reference divider is 2, the computed rate
>>>> becomes twice the actual output.
>>>>
>>>> Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
>>>> applying the 2 * FACTOR scaling. This yields the correct rate calculation:
>>>> rate = (parent_rate / ref_div) * 2 * factor.
>>>>
>>>> Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
>>>> IPQ5424, IPQ5018) that use ref_div = 1.
>>>
>>> I'm not sure how to interpret this. Is the value fixed on these platforms
>>> you mentioned, and always shows up as 0?
>>>
>>> Konrad
>>
>> On these platforms the hardware ref_div register comes up with a value
>> of 1 by default. It is, however, still a programmable field and not
>> strictly fixed to 1.
>>
>> The ref_div == 0 check in this patch is only meant as a safety net to
>> avoid a divide‑by‑zero in the rate calculation.
> 
> I think some sort of a warning/bugsplat would be good to have here,
> however I see that clk-rcg2.c : clk_gfx3d_determine_rate() apparently
> also silently fixes up a div0..
> 
> Konrad

I agree it would be better to at least flag this as an invalid
configuration. I can update the code to emit a warning (e.g. WARN_ON
(!ref_div) while still clamping ref_div to a sane value to avoid
crashing in production. That way we preserve the safety net but also
get some visibility if this ever happens.