Re: [PATCH v6 6/9] dt-bindings: arm: add an interrupt property for Coresight CTCU

From: Jie Gan

Date: Wed Dec 03 2025 - 21:49:37 EST




On 12/3/2025 10:30 PM, Mike Leach wrote:
On Mon, 8 Sept 2025 at 03:02, Jie Gan <jie.gan@xxxxxxxxxxxxxxxx> wrote:

Add an interrupt property to CTCU device. The interrupt will be triggered
when the data size in the ETR buffer exceeds the threshold of the
BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
of CTCU device will enable the interrupt.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Signed-off-by: Jie Gan <jie.gan@xxxxxxxxxxxxxxxx>
---
.../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
index 843b52eaf872..ea05ad8f3dd3 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
@@ -39,6 +39,16 @@ properties:
items:
- const: apb

+ interrupts:
+ items:
+ - description: Byte cntr interrupt for etr0
+ - description: Byte cntr interrupt for etr1
+
+ interrupt-names:
+ items:
+ - const: etr0
+ - const: etr1
+
in-ports:
$ref: /schemas/graph.yaml#/properties/ports

@@ -56,6 +66,8 @@ additionalProperties: false

examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
ctcu@1001000 {
compatible = "qcom,sa8775p-ctcu";
reg = <0x1001000 0x1000>;
@@ -63,6 +75,11 @@ examples:
clocks = <&aoss_qmp>;
clock-names = "apb";

+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "etr0",
+ "etr1";
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;

--
2.34.1

Not sure if you need me to review this purely DT hardware description
update but...

Hi Mike,

I am very glad to have you for reviewing, appreciate for your time.

Thanks,
Jie


Reviewed-by: Mike Leach <mike.leach@xxxxxxxxxx>