Re: [PATCH v6 2/2] bus: mhi: host: pci: Enable IP_SW1, IP_ETH0 and IP_ETH1 channels for QDU100

[Jakub Kicinski]

On Tue, 09 Dec 2025 16:55:39 +0530 Vivek Pernamitta wrote:
> Enable IP_SW1, IP_ETH0 and IP_ETH1 channels for M-plane, NETCONF and
> S-plane interface for QDU100.
> 
> Signed-off-by: Vivek Pernamitta <vivek.pernamitta@xxxxxxxxxxxxxxxx>
> ---
>  drivers/bus/mhi/host/pci_generic.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
> index e3bc737313a2f0658bc9b9c4f7d85258aec2474c..b64b155e4bd70326fed0aa86f32d8502da2f49d0 100644
> --- a/drivers/bus/mhi/host/pci_generic.c
> +++ b/drivers/bus/mhi/host/pci_generic.c
> @@ -269,6 +269,13 @@ static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = {
>  	MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4),
>  	MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5),
>  	MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5),
> +	MHI_CHANNEL_CONFIG_UL(48, "IP_SW1", 256, 6),
> +	MHI_CHANNEL_CONFIG_DL(49, "IP_SW1", 256, 6),
> +	MHI_CHANNEL_CONFIG_UL(50, "IP_ETH0", 256, 7),
> +	MHI_CHANNEL_CONFIG_DL(51, "IP_ETH0", 256, 7),
> +	MHI_CHANNEL_CONFIG_UL(52, "IP_ETH1", 256, 8),
> +	MHI_CHANNEL_CONFIG_DL(53, "IP_ETH1", 256, 8),

What is this CHANNEL_CONFIG thing and why is it part of the bus code
and not driver code? Having to modify the bus for driver changes
indicates the abstractions aren't used properly here..