Re: [RFC PATCH 01/10] spi: spi-mem: Introduce support for tuning controller

[Santhosh Kumar K]

On 03/12/25 19:42, Michael Walle wrote:
> On Wed Dec 3, 2025 at 10:50 AM CET, Miquel Raynal wrote:
> > > > > I think we should start with the requirement to have the pattern flashed
> > > > > already and figure out how SPI NOR or SPI NAND can discover that
> > > > > (perhaps via NVMEM?).
> > >
> > > But we should also keep in mind that certain flashes might return
> > > tuning data during the dummy cycles. I.e. the PHY might probably be
> > > tuned on each read and there is no need for any pre-programmed
> > > pattern.
> > >
> > > I'm not saying it should be implemented, but the current
> > > implementation should be that flexible that it will be easy to add
> > > that later.
> >
> > Conceptually, yes, but in practice, I know no controller capable of
> > using just a few cycles every transfer to calibrate themselves
> > automatically and reaching such an optimized speed state as the cadence
> > controller is capable of ATM.
>
> Then have a look at the flexspi controller. I.e. look at the LS1028A
> reference manual "18.5.15.1 Data Learning with Flash providing
> preamble bit".  The sequence is a follows:
>
> <CMD> <ADDR> <MODE> <DUMMY> <LEARN> <READ>
>
> There's an example with the learning pattern as short as 8 bit, or
> - I guess - 8 clock cycles.

In this case, we can skip calling execute_tuning, since *_exec_op
would be able to perform the necessary tuning, right?

Regards,
Santhosh.

> > Despite the end result being close, I would still consider this other
> > way to optimize the I/Os somewhat orthogonal. If someone has some
> > knowledge to share about the training patterns sent during the dummy
> > cycles, I am all ears though.
>
> There's also a short chapter about the training. Basically, it will
> just compare the read bits with a predefined value (which is max
> 32 bit long) of 16 different clock phases. Which one is chosen is
> not answered though (ideally it should be the one at the center of
> all matching clock phases).
>
> Now how good that tuning actually is, I don't know. But the
> procedure sounds sane. I'm also not sure whether this (any?) tuning
> will account for different I/O trace lengths of if it is assumed
> that they have to be trace length matched for multi IO flashes.
>
> -michael