RE: [Intel-wired-lan] [PATCH RFC net-next 13/13] ice: dpll: Support E825-C SyncE and dynamic pin discovery

[Ivan Vecera]

On December 12, 2025 11:20:43 AM GMT+01:00, "Loktionov, Aleksandr" <aleksandr.loktionov@xxxxxxxxx> wrote:
>
>
>> -----Original Message-----
>> From: Intel-wired-lan <intel-wired-lan-bounces@xxxxxxxxxx> On Behalf
>> Of Ivan Vecera
>> Sent: Thursday, December 11, 2025 8:48 PM
>> To: netdev@xxxxxxxxxxxxxxx; Andrew Lunn <andrew+netdev@xxxxxxx>;
>> David S. Miller <davem@xxxxxxxxxxxxx>; Eric Dumazet
>> <edumazet@xxxxxxxxxx>; Jakub Kicinski <kuba@xxxxxxxxxx>; Paolo Abeni
>> <pabeni@xxxxxxxxxx>; Rob Herring <robh@xxxxxxxxxx>; Krzysztof
>> Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley <conor+dt@xxxxxxxxxx>;
>> Vadim Fedorenko <vadim.fedorenko@xxxxxxxxx>; Kubalewski, Arkadiusz
>> <arkadiusz.kubalewski@xxxxxxxxx>; Nitka, Grzegorz
>> <grzegorz.nitka@xxxxxxxxx>; Jiri Pirko <jiri@xxxxxxxxxxx>; Oros,
>> Petr <poros@xxxxxxxxxx>; Schmidt, Michal <mschmidt@xxxxxxxxxx>;
>> Prathosh Satish <Prathosh.Satish@xxxxxxxxxxxxx>; Nguyen, Anthony L
>> <anthony.l.nguyen@xxxxxxxxx>; Kitszel, Przemyslaw
>> <przemyslaw.kitszel@xxxxxxxxx>; Saeed Mahameed <saeedm@xxxxxxxxxx>;
>> Leon Romanovsky <leon@xxxxxxxxxx>; Tariq Toukan <tariqt@xxxxxxxxxx>;
>> Mark Bloch <mbloch@xxxxxxxxxx>; Richard Cochran
>> <richardcochran@xxxxxxxxx>; Jonathan Lemon
>> <jonathan.lemon@xxxxxxxxx>; Simon Horman <horms@xxxxxxxxxx>;
>> Lobakin, Aleksander <aleksander.lobakin@xxxxxxxxx>; Willem de Bruijn
>> <willemb@xxxxxxxxxx>; Stefan Wahren <wahrenst@xxxxxxx>;
>> devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; intel-
>> wired-lan@xxxxxxxxxxxxxxxx; linux-rdma@xxxxxxxxxxxxxxx
>> Subject: [Intel-wired-lan] [PATCH RFC net-next 13/13] ice: dpll:
>> Support E825-C SyncE and dynamic pin discovery
>> 
>> From: Arkadiusz Kubalewski <arkadiusz.kubalewski@xxxxxxxxx>
>> 
>> Add DPLL support for the Intel E825-C Ethernet controller. Unlike
>> previous
>> generations (E810), the E825-C connects to the platform's DPLL
>> subsystem
>> via MUX pins defined in the system firmware (Device Tree/ACPI).
>> 
>> Implement the following mechanisms to support this architecture:
>> 
>> 1. Dynamic Pin Discovery: Use the fwnode_dpll_pin_find() helper to
>>    locate the parent MUX pins defined in the firmware.
>> 
>> 2. Asynchronous Registration: Since the platform DPLL driver may
>> probe
>>    independently of the network driver, utilize the DPLL notifier
>> chain
>>    (register_dpll_notifier). The driver listens for DPLL_PIN_CREATED
>>    events to detect when the parent MUX pins become available, then
>>    registers its own Recovered Clock (RCLK) and PTP (1588) pins as
>> children
>>    of those parents.
>> 
>> 3. Hardware Configuration: Implement the specific register access
>> logic
>>    for E825-C CGU (Clock Generation Unit) registers (R10, R11). This
>>    includes configuring the bypass MUXes and clock dividers required
>> to
>>    drive SyncE and PTP signals.
>> 
>> 4. Split Initialization: Refactor `ice_dpll_init()` to separate the
>>    static initialization path of E810 from the dynamic, firmware-
>> driven
>>    path required for E825-C.
>> 
>> Co-developed-by: Ivan Vecera <ivecera@xxxxxxxxxx>
>> Co-developed-by: Grzegorz Nitka <grzegorz.nitka@xxxxxxxxx>
>> Signed-off-by: Ivan Vecera <ivecera@xxxxxxxxxx>
>> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@xxxxxxxxx>
>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@xxxxxxxxx>
>> ---
>>  drivers/net/ethernet/intel/ice/ice_dpll.c   | 964
>> ++++++++++++++++++--
>>  drivers/net/ethernet/intel/ice/ice_dpll.h   |  29 +
>>  drivers/net/ethernet/intel/ice/ice_lib.c    |   3 +
>>  drivers/net/ethernet/intel/ice/ice_ptp.c    |  29 +
>>  drivers/net/ethernet/intel/ice/ice_ptp_hw.c |   9 +-
>>  drivers/net/ethernet/intel/ice/ice_ptp_hw.h |   1 +
>>  drivers/net/ethernet/intel/ice/ice_tspll.c  | 223 +++++
>>  drivers/net/ethernet/intel/ice/ice_tspll.h  |  14 +-
>>  drivers/net/ethernet/intel/ice/ice_type.h   |   6 +
>>  9 files changed, 1188 insertions(+), 90 deletions(-)
>> 
>> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
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>...
>
>> +static int
>> +ice_dpll_pin_get_parent_num(struct ice_dpll_pin *pin,
>> +			    const struct dpll_pin *parent)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; pin->num_parents; i++)
>> +		if (pin->pf->dplls.inputs[pin->parent_idx[i]].pin ==
>> parent)
>Oh, no! we don't need a 2nd Infinite Loop in Cupertino!

Oops, thanks for pointing out... During testing the parent
was always found so this didn't cause any problem.

Of course I will fix it. 😉
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>...
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>> --
>> 2.51.2
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