Re: [PATCH v6 1/5] media: dt-bindings: Add CAMSS device for Kaanapali

[Vijay Kumar Tumati]

On 12/12/2025 4:49 AM, Vladimir Zapolskiy wrote:
> On 11/18/25 20:44, Konrad Dybcio wrote:
> > On 11/18/25 7:25 PM, Vijay Kumar Tumati wrote:
> > > On 11/18/2025 7:00 AM, Bryan O'Donoghue wrote:
> > > > On 14/11/2025 03:29, Hangxiang Ma wrote:
> > > > > +                  <0x0 0x0900e000 0x0 0x1000>,
> > > >
> > > > Why aren't you starting @ 0x0900e000 ? seems to be omitting some of 
> > > > the registers in the ICP block. Should start at +0xd000 not +0xe000 ?
> > > >
> > > > > +                  <0x0 0x0902e000 0x0 0x1000>,
> > > >
> > > > Same here.
> > > Hi Bryan, HLOS does not have access to those registers. They are 
> > > configured by the Hyp.
> >
> > If that's hyp, please add them. We already have platforms without
> > Gunyah. Remember, bindings are defined once and for good and I wouldn't
> > call it impossible that someone would want to run that configuration on
> > Kaanapali some day
>
> If the ICP register block is added now, then it will practically exclude
> an option to run hardware demosaic on Kaanapali. There were notorious
> and still unresolved problems with CSIPHY blocks, which shall be split
> from CSID/VFE CAMSS on device tree level also, for similar reasons the
> same should be done with ICP or other blocks. It makes exactly zero
> sense to pile everything into a monolythic device tree node, and doing
> so undermines any future advances in CAMSS support in the upstream
> Linux, the hardware description in downstream is done thoughtfully 
> better,
> and not for no reason.
Hi Vladimir, yes, this has been discussed in the past and the general 
consensus from everyone is for not blocking KNP series on this. But yes, 
there is an ongoing effort to modularize the bindings for future 
chipsets and when it's ready, we can review, discuss and take it 
forward. As for your ICP concern, if you are referring to the Demosaic 
in OFE, I believe we might still be able to do it either with direct OFE 
config from CPU or using the firmware (preferred), given that we 
properly establish the shared memory and SID IOVA ranges for ICP, 
assuming that the load and authenticate will be taken care by Hyp or TZ. 
Please share your thoughts if I missed something.

Hi Bryan, please feel free to add your thoughts.

Thanks,

Vijay.