[tip: perf/core] perf/x86/intel: Add Airmont NP

[tip-bot2 for Martin Schiller]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     a08340fd291671c54d379d285b2325490ce90ddd
Gitweb:        https://git.kernel.org/tip/a08340fd291671c54d379d285b2325490ce90ddd
Author:        Martin Schiller <ms@xxxxxxxxxx>
AuthorDate:    Mon, 24 Nov 2025 08:48:45 +01:00
Committer:     Peter Zijlstra <peterz@xxxxxxxxxxxxx>
CommitterDate: Wed, 17 Dec 2025 13:31:08 +01:00

perf/x86/intel: Add Airmont NP

The Intel / MaxLinear Airmont NP (aka Lightning Mountain) supports the
same architectual and non-architecural events as Airmont.

Signed-off-by: Martin Schiller <ms@xxxxxxxxxx>
Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
Reviewed-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
Link: https://patch.msgid.link/20251124074846.9653-3-ms@xxxxxxxxxx
---
 arch/x86/events/intel/core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 0553c11..1840ca1 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -7410,6 +7410,7 @@ __init int intel_pmu_init(void)
 	case INTEL_ATOM_SILVERMONT_D:
 	case INTEL_ATOM_SILVERMONT_MID:
 	case INTEL_ATOM_AIRMONT:
+	case INTEL_ATOM_AIRMONT_NP:
 	case INTEL_ATOM_SILVERMONT_MID2:
 		memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
 			sizeof(hw_cache_event_ids));