Re: [PATCH v3 0/2] soc: qcom: llcc: Add support for Glymur SoC

[Bjorn Andersson]

On Thu, 11 Dec 2025 14:32:34 +0530, Pankaj Patil wrote:
> Glymur SoC uses the Last Level Cache Controller (LLCC) as its
> system cache controller, update the device-tree bindings to allow
> maximum of 14 registers for llcc block since GLymur has 12 llcc base
> register regions and an additional AND, OR broadcast base register.
> Updated SCT configuration data in the LLCC driver.
> 
> Enabled additional use case IDs defined in
> include/linux/soc/qcom/llcc-qcom.h:
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
      commit: bd0b8028ce5fbc7d9f5c2751c20661b0d8114e60
[2/2] soc: qcom: llcc-qcom: Add support for Glymur
      commit: 0418592550c6a370b2b8a5cbebd53fb7dd63d837

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>