Re: [PATCH v3 1/6] clk: correct clk_div_mask() return value for width == 32
From: Brian Masney
Date: Mon Dec 22 2025 - 13:48:53 EST
On Tue, Dec 16, 2025 at 11:39:41AM +0800, Junhui Liu wrote:
> The macro clk_div_mask() currently wraps to zero when width is 32 due to
> 1 << 32 being undefined behavior. This leads to incorrect mask generation
> and prevents correct retrieval of register field values for 32-bit-wide
> dividers.
>
> Although it is unlikely to exhaust all U32_MAX div, some clock IPs may rely
> on a 32-bit val entry in their div_table to match a div, so providing a
> full 32-bit mask is necessary.
>
> Fix this by casting 1 to long, ensuring proper behavior for valid widths up
> to 32.
>
> Reviewed-by: Troy Mitchell <troy.mitchell@xxxxxxxxxxxxxxxxxx>
> Signed-off-by: Junhui Liu <junhui.liu@xxxxxxxxxxxxx>
Reviewed-by: Brian Masney <bmasney@xxxxxxxxxx>