[PATCH v2 0/2] Fixup HDMI PLL for phy-rockchip-samsung-hdptx

[Cristian Ciocaltea]

The Samsung HDMI/eDP TX PHY is currently not able to provide an accurate
enough PLL output frequency to match the TMDS rate of a 1080p@120Hz
display mode, when used with 10 bpc RGB.

This patch set adds a new entry to the TMDS configuration table,
providing the necessary frequency division coefficients for the PHY PLL
to generate the expected 461.101250 MHz output.

Additionally, it drops a bunch of unused members from struct
ropll_config and makes the configuration table more readable.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>
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Changes in v2:
- Dropped one more unused member from struct ropll_config (sdm_clk_div)
- Swapped the TMDS config entry corresponding to the 108000000ULL rate
  with 106500000ULL, to fix an unspotted ordering issue
- Collected Tested-by tag from Derek
- Rebased series onto v6.19-rc1
- Link to v1: https://lore.kernel.org/r/20251204-phy-hdptx-pll-fix-v1-0-d94fd6cfd59b@xxxxxxxxxxxxx

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Cristian Ciocaltea (2):
      phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output
      phy: rockchip: samsung-hdptx: Cleanup TMDS PLL config table

 drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 80 +++++++----------------
 1 file changed, 24 insertions(+), 56 deletions(-)
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base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20251204-phy-hdptx-pll-fix-0787c92e0cfe