[PATCH 1/2] arm64: dts: qcom: x1p42100-lenovo-thinkbook-16: force usb2-only mode on usb_1_ss2_dwc3

[Jens Glathe via B4 Relay]

From: Jens Glathe <jens.glathe@xxxxxxxxxxxxxxxxxxxxxx>

The usb_1_ss2 complex has 2 phys, usb_1_ss2_hsphy and usb_1_ss2_qmpphy. On this
laptop, they are used for different peripherals: The hsphy for the fingerprint
reader, the qmpphy to drive a hdmi bridge. The normal logical wiring for the dwc3
controller is to both phys. Overwrite that with ports only to the hsphy.

Signed-off-by: Jens Glathe <jens.glathe@xxxxxxxxxxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
index 3186e79e862de67cbda48a4b85a459e6e965ba65..b505a4cbb4350a962bbf779ec788265c7583bf20 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
+++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
@@ -1560,6 +1560,20 @@ &usb_1_ss2_dwc3 {
 	maximum-speed = "high-speed";
 	phys = <&usb_1_ss2_hsphy>;
 	phy-names = "usb2-phy";
+
+	/delete-property/ ports;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			usb_1_ss2_dwc3_hs: endpoint {
+			};
+		};
+	};
 };
 
 &usb_1_ss2_hsphy {

-- 
2.51.0